Microprocessor configuration with encryption

• US 20030005313A1
• Filed: 07/18/2002
• Published: 01/02/2003
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Sedlak, Holger, Gammel, Berndt, Kniffler, Oliver
• Granted Patent: US 7,269,742 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

Claims

1. A microprocessor configuration, comprising:

a central processing unit;

a functional unit;

a memory unit;

each of said central processing unit, said memory unit, and said functional unit having a first encryption unit with;

a first means for providing an alterable key; and

a first combinational logic element;

said memory unit having a second encryption unit with;

a second means for providing a key; and

a second combinational logic element;

a bus;

said first encryption unit connecting said central processing unit to said bus;

said second encryption unit connecting said functional unit to said bus;

said third encryption unit connecting said memory unit to said bus;

said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging data therebetween; and

said second combinational logic element connected between said first alterable key providing means and said first combinational logic element.

2. The microprocessor configuration according to claim 1, wherein:

said first alterable key providing means has;

a register with an output connected to said first combinational logic element; and

an input side; and

a key generator is connected to said input side of said first alterable key providing means of each of said first encryption units.

3. The microprocessor configuration according to claim 2, wherein said key generator is a random number generator adapted to randomly generate binary numbers.

4. The microprocessor configuration according to claim 3, including a clock generator, said register of each of said first encryption units being commonly controlled by said clock generator.

5. The microprocessor configuration according to claim 3, wherein said register of each of said first encryption units is adapted to be controlled by a common clock generator.

6. The microprocessor configuration according to claim 2, wherein:

said first combinational logic element has an input;

said second combinational logic element has inputs;

said second key providing means has a register with an input and an output;

a second key generator is connected to said input of said register of said second key providing means;

a respective one of said inputs of said second combinational logic element is connected to;

said output of said register of said second key providing means; and

said register of said first alterable key providing means; and

said output of said second combinational logic element is connected to said input of said first combinational logic element.

7. The microprocessor configuration according to claim 6, wherein:

a respective one of said inputs of said second combinational logic element is connected to;

said output of said register of said second key providing means; and

said register of said first alterable key providing means of said memory unit; and

said output of said second combinational logic element is connected to an input of said first combinational logic element of said memory unit.

8. The microprocessor configuration according to claim 1, wherein said first combinational logic element is an Exclusive-OR-gate.

9. The microprocessor configuration according to claim 1, wherein said second combinational logic element is an Exclusive-OR-gate.

10. The microprocessor configuration according to claim 8, wherein said second combinational logic element is an Exclusive-OR-gate.

11. The microprocessor configuration according to claim 1, wherein said memory unit is a volatile memory.

12. The microprocessor configuration according to claim 6, wherein said second key generator is adapted to generate a new key when said memory unit has no valid memory content.

13. The microprocessor configuration according to claim 12, where said second key generator is adapted to generate a key after said memory unit has been initialized.

14. The microprocessor configuration according to claim 1, including a second memory unit connected to said bus, said memory unit being a cache buffering data for said second memory unit.

15. The microprocessor configuration according to claim 1, wherein:

said functional unit is a second memory unit; and

said memory unit is a cache buffering data for said second memory unit.

16. The microprocessor configuration according to claim 1, wherein said second key providing means is a second alterable key providing means.

18. The microprocessor configuration according to claim 17, wherein:

said alterable key providing device has;

a register with an output connected to said first combinational logic element; and

an input side; and

a key generator is connected to said input side of said alterable key providing device of each of said first encryption units.

19. The microprocessor configuration according to claim 18, wherein said key generator is a random number generator adapted to randomly generate binary numbers.

20. The microprocessor configuration according to claim 19, including a clock generator, said register of each of said first encryption units being commonly controlled by said clock generator.

21. The microprocessor configuration according to claim 19, wherein said register of each of said first encryption units is adapted to be controlled by a common clock generator.

22. The microprocessor configuration according to claim 18, wherein:

said first combinational logic element has an input;

said second combinational logic element has inputs;

said key providing device has a register with an input and an output;

a second key generator is connected to said input of said register of said key providing device;

a respective one of said inputs of said second combinational logic element is connected to;

said output of said register of said key providing device; and

said register of said alterable key providing device; and

said output of said second combinational logic element is connected to said input of said first combinational logic element.

23. The microprocessor configuration according to claim 1, wherein:

a respective one of said inputs of said second combinational logic element is connected to;

said output of said register of said key providing device; and

said register of said alterable key providing device of said memory unit; and

said output of said second combinational logic element is connected to an input of said first combinational logic element of said memory unit.

24. The microprocessor configuration according to claim 17, wherein said first combinational logic element is an Exclusive-OR-gate.

25. The microprocessor configuration according to claim 17, wherein said second combinational logic element is an Exclusive-OR-gate.

26. The microprocessor configuration according to claim 24, wherein said second combinational logic element is an Exclusive-OR-gate.

27. The microprocessor configuration according to claim 17, wherein said memory unit is a volatile memory.

28. The microprocessor configuration according to claim 22, wherein said second key generator is adapted to generate a new key when said memory unit has no valid memory content.

29. The microprocessor configuration according to claim 22, where said second key generator is adapted to generate a key after said memory unit has been initialized.

30. The microprocessor configuration according to claim 17, including a second memory unit connected to said bus, said memory unit being a cache buffering data for said second memory unit.

31. The microprocessor configuration according to claim 17, wherein:

said functional unit is a second memory unit; and

said memory unit is-a cache buffering data for said second memory unit.

32. The microprocessor configuration according to claim 17, wherein said key providing device is a second key providing device.

17. A microprocessor configuration, comprising:

a central processing unit;

a functional unit;

a memory unit;

each of said central processing unit, said memory unit, and said functional unit having a first encryption unit with;

an alterable key providing device; and

a first combinational logic element;

said memory unit having a second encryption unit with;

a key providing device; and

a second combinational logic element;

a bus;

said first encryption unit connecting said central processing unit to said bus;

said second encryption unit connecting said functional unit to said bus;

said third encryption unit connecting said memory unit to said bus;

said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging data therebetween; and

said second combinational logic element connected between said alterable key providing device and said first combinational logic element.