Microprocessor configuration with encryption
First Claim
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1. A microprocessor configuration, comprising:
- a central processing unit;
a functional unit;
a memory unit;
said central processing unit, said memory unit, and said functional unit each having a first encryption unit with;
a first means for providing an alterable key being the same in said first encryption unit for each of said central processing unit, said memory unit and said functional unit; and
a first combinational logic element;
said memory unit having a second encryption unit with;
a second means for providing a key; and
a second combinational logic element;
a bus receiving alterable key encrypted data from said central processing unit, said memory unit, and said functional unit;
said first encryption unit of said central processing unit directly connecting said central processing unit to said bussaid first encryption unit of said functional unit directly connecting said functional unit to said bus;
said first encryption unit of said memory unit directly connecting said memory unit to said bus;
said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging the alterable key encrypted data therebetween, the alterable key encrypted data transmitted by said bus and sent to said memory unit being decrypted using the alterable key and encrypted using the key, resulting in key encrypted data, and the key encrypted data transmitted from said memory unit and sent to said bus being decrypted using the key and encrypted using the alterable key resulting in the alterable key encrypted data; and
said second combinational logic element connected between said second means and said first combinational logic element of said first encryption unit of said memory unit.
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Abstract
A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.
24 Citations
33 Claims
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1. A microprocessor configuration, comprising:
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a central processing unit; a functional unit; a memory unit; said central processing unit, said memory unit, and said functional unit each having a first encryption unit with; a first means for providing an alterable key being the same in said first encryption unit for each of said central processing unit, said memory unit and said functional unit; and a first combinational logic element; said memory unit having a second encryption unit with; a second means for providing a key; and a second combinational logic element; a bus receiving alterable key encrypted data from said central processing unit, said memory unit, and said functional unit; said first encryption unit of said central processing unit directly connecting said central processing unit to said bus said first encryption unit of said functional unit directly connecting said functional unit to said bus; said first encryption unit of said memory unit directly connecting said memory unit to said bus; said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging the alterable key encrypted data therebetween, the alterable key encrypted data transmitted by said bus and sent to said memory unit being decrypted using the alterable key and encrypted using the key, resulting in key encrypted data, and the key encrypted data transmitted from said memory unit and sent to said bus being decrypted using the key and encrypted using the alterable key resulting in the alterable key encrypted data; and said second combinational logic element connected between said second means and said first combinational logic element of said first encryption unit of said memory unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A microprocessor configuration, comprising:
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a central processing unit; a functional unit; a memory unit; said central processing unit, said memory unit, and said functional unit each having a first encryption unit with; an alterable key providing device, said alterable key being the same in said first encryption unit for each of said central processing unit, said memory unit and said functional unit; and a first combinational logic element; said memory unit having a second encryption unit with; a key providing device; and a second combinational logic element; a bus receiving alterable key encrypted data from said central processing unit, said memory unit, and said functional unit; said first encryption unit of said central processing unit directly connecting said central processing unit to said bus; said first encryption unit of said functional unit directly connecting said functional unit to said bus; said first encryption unit of said memory unit directly connecting said memory unit to said bus; said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging the alterable key encrypted data therebetween, the alterable key encrypted data transmitted by said bus and sent to said memory unit being simultaneously decrypted using said alterable key providing device and encrypted using said key providing device resulting in key encrypted data, and the key encrypted data transmitted from said memory unit and sent to said bus being simultaneously decrypted using said key providing device and encrypted using said alterable key providing device resulting in the alterable key encrypted data; and said second combinational logic element connected between said alterable key providing device and said first combinational logic element of said first encryption unit of said memory unit. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A microprocessor configuration, comprising:
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a central processing unit; a functional unit; a memory unit; said central processing unit, said memory unit, and said functional unit each having a first encryption unit with; a first means for providing an alterable key being the same in said first encryption unit for each of said central processing unit, said memory unit and said functional unit; and a first combinational logic element having an input; said memory unit having a second encryption unit with; a second means for providing a key and having an output; and a second combinational logic element having a first input, a second input and an output; a bus receiving alterable key encrypted data from said central processing unit, said memory unit, and said functional unit; said first encryption unit of said central processing unit directly connecting said central processing unit to said bus; said first encryption unit of said functional unit directly connecting said functional unit to said bus; said first encryption unit of said memory unit directly connecting said memory unit to said bus; said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging the alterable key encrypted data therebetween, the alterable key encrypted data transmitted by said bus and sent to said memory unit being decrypted using the alterable key and encrypted using the key, resulting in key encrypted data, and the key encrypted data transmitted from said memory unit and sent to said bus being decrypted using the key and encrypted using the alterable key resulting in the alterable key encrypted data; and said second combinational logic element connected between said second means and said first combinational logic element of said first encryption unit of said memory unit, said output of said second combinational logic element is connected to said input of said first combinational logic element; said output of said first means of said memory unit connected to said first input of said second combination logic element; and said output of said second means of said memory unit connected to said second input of said second combination logic element.
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Specification