System for simplifying the programmable memory to logic interface in FPGA

• US 20030005402A1
• Filed: 06/28/2002
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: HD Silicon Solutions LLC (f/k/a Innovative Silicon Solutions, LLC)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Bal, Ankur
• Granted Patent: US 6,748,577 B2
• Time in Patent Office: Days
• US Class Current: 716/16
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Claims

1. A system for simplifying the interface between the embedded memory and the programmable logic blocks and input output resources in an FPGA, comprising:

an interface to isolate the general purpose routing architecture or intra-PLB (programmable logic blocks) routing from memory address, data and control lines; and

means for connecting said programmable logic blocks (PLBs) and input-output (IO) resources of the FPGA to the embedded memory or RAM using multiple dedicated direct interconnects.

2. A system as claimed in claim 1 wherein the direct interconnects connecting to the input pins of the memory are tapped from Programmable Logic Blocks (PLBs) output in vicinity of the memory blocks and the output pins of memory are directly connected to the input of programmable Logic Blocks (PLBs) in the neighborhood of the memory block.

3. A system as claimed in claim 1 wherein the direct interconnects are not a part of general routing resources of the FPGA and thus do not hamper the symmetric routing fabric for the logic resources or the programmable logic blocks (PLBs).

4. A system as claimed in claim 5 wherein said memory has a plurality of multiplexers and de-multiplexers at its input and output pins respectively.

5. A system as claimed in claim 6 wherein, the input to the multiplexer are output from various programmable logic blocks(PLBs) or even the same programmable Logic Blocks (PLBs) or from input-output (IO) pads/routing;

and

the output from the de-multiplexer are connected to programmable logic blocks (PLBs) inputs or input-output (IO) resources.

6. A system as claimed in claim 1 wherein Programmable Logic Blocks (PLBs) interact with said memory only through programmable tappings to/from their inputs and outputs.

7. A system as claimed in claim 1 further comprising devoted bus based routing for clubbing data and address lines, in order to combine the memory blocks to implement larger memories to reduce configuration register or flip flop count against a net-to-net route.

8. A system as claimed in claim 1 wherein the registers internal to said memory blocks are eliminated by utilizing the registers or flip flops of said PLBs for latching signals sent to or received from said memory, thereby saving significant chip area.

9. A system as claimed in claim 8 wherein said registers internal to said memory include input registers or output registers or both.

10. A system as claimed in claim 8 wherein said internal registers or flip-flops of said PLBs can also receive inputs from the general purpose routing.

11. A system as claimed in claim 1 wherein the internal elements of said PLBs including the LUT and the internal Flip Flop can also be used for other functionality independent of the memory interface.

12. A system as claimed in claim 10 wherein said registers or flip-flops are selectively bypassed for the case when unregistered memory inputs and outputs are required.

13. A system as claimed in claim 1 wherein said memory is ROM or RAM.

14. A system as claimed in claim 1 wherein the connectivity of said PLBs and IO resources with the General Purpose routing architecture coexists with said interface with said embedded memory.

15. A system as claimed in claim 1 wherein the output registers internal to said memory blocks are eliminated by utilizing the registers of said PLBs for latching the output data from said memory, thereby saving significant chip area.

17. A method as claimed in claim 13 including:

tapping of direct interconnects to the input pins of the memory from Programmable Logic Blocks (PLBs) output in vicinity of the memory blocks, and

connecting output pins of memory directly to the input of programmable Logic Blocks (PLBs) in the neighborhood of the memory block.

18. A method as claimed in claim 13 wherein the direct interconnects are not a part of general routing resources of the FPGA and thus do not hamper the symmetric routing fabric for the logic resources or the programmable logic blocks (PLBs).

19. A method as claimed in claim 15 incorporating a simple single port memory with a plurality of multiplexer and de-multiplexer at the input and output pins respectively.

20. A method as claimed in claim 16 including:

connecting inputs to said multiplexer to outputs from various programmable logic blocks(PLBs) or even the same programmable Logic Blocks (PLBs) or from input-output (IO) pads/routing; and

connecting outputs from the de-multiplexer to programmable logic blocks (PLBs) inputs or input-output (IO) resources.

21. A method as claimed in claim 13 including restricting the interaction of Programmable Logic Blocks (PLBs) with memory only through programmable tapings to/from their inputs and outputs.

22. A method as claimed in claim 13 further incorporating devoted bus based routing for clubbing data and address lines, in order to combine the memory blocks to implement larger memories to reduce configuration register or flip flops count against a net-to-net route.

23. A method as claimed in claim 13 wherein the registers internal to said memory blocks are eliminated by utilizing the registers or flip flops of said PLBs for latching signals sent to or received from said memory, thereby saving significant chip area.

24. A method as claimed in claim 23 wherein said registers internal to said memory include input registers or output registers or both.

25. A method as claimed in claim 23 wherein said internal registers or flip-flops of said PLBs can also receive inputs from the general purpose routing.

26. A method as claimed in claim 13 wherein the internal elements of said PLBs including the LUT and the internal flip flop can also be used for other functionality independent of the memory interface.

27. A method as claimed in claim 20 including selective bypassing of said registers or flip flops for the case when unregistered memory outputs are required.

28. A method as claimed in claim 13 wherein said memory is ROM or RAM.

29. A method as claimed in claim 13 wherein the connectivity of said PLBs and IO resources with the general purpose routing architecture coexists with said interface with said embedded memory.

30. A method as claimed in claim 13 wherein the output registers internal to said memory blocks are eliminated by utilizing the registers of said PLBs for latching the output data from said memory, thereby saving significant chip area.

16. A method for simplifying the interface between the embedded memory and the programmable logic blocks and input output resources in an FPGA, comprising:

isolating the general purpose routing architecture or intra-PLB (programmable logic blocks) routing from memory address, data and control lines; and

connecting said programmable logic blocks (PLBs) and input-output (IO) resources of the FPGA to the embedded memory or memory using multiple dedicated direct interconnects.