Computer system having a single processor equipped to serve as multiple logical processors for pre-boot software to execute pre-boot tasks in parallel

• US 20030009654A1
• Filed: 06/29/2001
• Published: 01/09/2003
• Est. Priority Date: 06/29/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mooney, Steven P., Siddioi, Faraz A., Nalawadi, Rajeev K.
• Application Number:
  US09/893,718
• Publication Number:
  US 20030009654A1
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computer system is provided with a single processor equipped to serve as multiple logical processors. The computer system comprises a host chipset connected to the processor; PCI devices connected to the host chipset, via a PCI bus; and a main storage connected to the host chipset and arranged to store an operating system (OS) and contain a basic input/output system (system BIOS) configured to execute multiple pre-boot tasks, including memory initialization and PCI bus initialization concurrently, on the processor which serve as multiple logical processors before passing control to the operating system (OS).

Claims

1. A computer system, comprising:

a processor equipped to serve as multiple logical processors;

a host chipset connected to the processor;

PCI devices connected to the host chipset, via a PCI bus; and

a main storage connected to the host chipset and arranged to store an operating system (OS) and contain a basic input/output system (system BIOS) configured to execute multiple pre-boot tasks, including memory initialization and PCI bus initialization concurrently, on the processor which serve as multiple logical processors before passing control to the operating system (OS).

2. The computer system as claimed in claim 1, wherein said main storage comprises:

a main memory arranged to store the operating system (OS) for use by the processor; and

a flash memory arranged to store the system BIOS and other applications that may execute during boot up (start-up) before the operating system (OS) is loaded.

3. The computer system as claimed in claim 1, wherein said processor equipped to serve as multiple logical processors allows the system BIOS to execute the memory initialization on one of the logical processors while enabling the other logical processor to proceed with PCI bus initialization tasks.

4. The computer system as claimed in claim 3, wherein said memory initialization is executed by:

detecting a physical memory array plugged into the computer system;

programming the host chipset with the physical memory specifics, and initializing the physical memory using the host chipset;

detecting a physical memory ECC (Error Checking and Correction) Capability; and

programming the host chipset with the ECC capability, and writing zeros to the entire physical memory array in order to ensure that memory is usable for the operating system (OS).

5. The computer system as claimed in claim 1, wherein said processor equipped to serve as multiple logical processors allows the system BIOS to execute the PCI bus initialization on one of the logical processors while enabling the other logical processor to proceed with other normal PCI device initialization tasks.

6. The computer system as claimed in claim 3, wherein said PCI bus initialization is executed by:

scanning all possible PCI buses connected to the host chipset;

after each PCI bus is scanned, scanning and initializing all possible PCI devices connected thereto on an individual basis;

after each PCI device is scanned, initializing all possible PCI functions assigned thereto on an individual function; and

terminating the PCI bus initialization, when all the PCI buses, all the PCI devices connected to each PCI bus, and all PCI functions assigned to each PCI device are scanned and initialized.

7. The computer system as claimed in claim 1, wherein said processor equipped to serve as multiple logical processors includes a Boot-Strap Logical Processor (BSLP) assigned to execute a set of pre-boot tasks and one or more Alternate Logical Processors (ALP) assigned to executed another set of pro-boot tasks concurrently until all assigned pre-boot tasks are completed before passing the control to the operating system (OS).

8. The computer system as claimed in claim 7, wherein, upon a system reset, said Boot-Strap Logical Processor (BSLP) executes the following pre-boot tasks:

detecting a physical memory, and programming the host chipset;

detecting the presence of all logical processors and sending a SIPI (Startup Inter-Processor Interrupt) to wake up the Alternate Logical Processor (ALP);

initializing all internal hardware of the host chipset, and all storage devices connected to the host chipset; and

waiting for ALP code execution completion to place the Alternate Logical Processor (ALP) in a wait state before passing the control to the operating system (OS).

9. The computer system as claimed in claim 8, wherein, upon receipt of the SIPI, said Alternate Logical Processor (ALP) executes the memory initialization and the PCI bus initialization respectively, while the Boot-Strap Logical Processor (BSLP) initializes all internal hardware of the host chipset and all storage devices connected to the host chipset, and after the memory initialization and PCI bus initialization are completed, indicates to the Boot-Strap Logical Processor (BSLP) that the memory initialization and PCI bus initialization are completed after all internal hardware of the host chipset and all storage devices connected to the host chipset are initialized by the Boot-Strap Logical Processor (BSLP).

10. The computer system as claimed in claim 9, wherein said memory initialization is executed by:

detecting a physical memory array plugged into the computer system;

programming the host chipset with the physical memory specifics, and initializing the physical memory using the host chipset;

detecting a physical memory ECC (Error Checking and Correction) Capability; and

programming the host chipset with the ECC capability, and writing zeros to the entire physical memory array in order to ensure that memory is usable for the operating system (OS).

11. The computer system as claimed in claim 9, wherein said PCI bus initialization is executed by:

scanning all possible PCI buses connected to the host chipset;

after each PCI bus is scanned, scanning and initializing all possible PCI devices connected thereto on an individual basis;

after each PCI device is scanned, initializing all possible PCI functions assigned thereto on an individual function; and

terminating the PCI bus initialization, when all the PCI buses, all the PCI devices connected to each PCI bus, and all PCI functions assigned to each PCI device are scanned and initialized.

13. The computer system as claimed in claim 12, wherein said processor equipped to serve as multiple logical processors allows the system BIOS to execute the memory initialization on one of the logical processors while enabling the other logical processor to proceed with PCI bus initialization tasks.

14. The computer system as claimed in claim 13, wherein said memory initialization is executed by:

detecting a physical memory array plugged into the computer system;

programming the host chipset with the physical memory specifics, and initializing the physical memory using the host chipset;

detecting a physical memory ECC (Error Checking and Correction) Capability; and

programming the host chipset with the ECC capability, and writing zeros to the entire physical memory array in order to ensure that memory is usable for the operating system (OS).

15. The computer system as claimed in claim 12, wherein said processor equipped to serve as multiple logical processors allows the system BIOS to execute the PCI bus initialization on one of the logical processors while enabling the other logical processor to proceed with other normal PCI device initialization tasks.

16. The computer system as claimed in claim 15, wherein said PCI bus initialization is executed by:

scanning all possible PCI buses connected to the host chipset;

after each PCI bus is scanned, scanning and initializing all possible PCI devices connected thereto on an individual basis;

after each PCI device is scanned, initializing all possible PCI functions assigned thereto on an individual function; and

terminating the PCI bus initialization, when all the PCI buses, all the PCI devices connected to each PCI bus, and all PCI functions assigned to each PCI device are scanned and initialized.

17. The computer system as claimed in claim 12, wherein said processor equipped to serve as multiple logical processors includes a Boot-Strap Logical Processor (BSLP) assigned to execute a set of pre-boot tasks and one or more Alternate Logical Processors (ALP) assigned to executed another set of pro-boot tasks concurrently until all assigned pre-boot tasks are completed before passing the control to the operating system (OS).

18. The computer system as claimed in claim 17, wherein, upon a system reset, said Boot-Strap Logical Processor (BSLP) executes the following pre-boot tasks:

detecting a physical memory, and programming the host chipset;

detecting the presence of all logical processors and sending a SIPI (Startup Inter-Processor Interrupt) to wake up the Alternate Logical Processor (ALP);

initializing all internal hardware of the host chipset, and all storage devices connected to the host chipset; and

waiting for ALP code execution completion to place the Alternate Logical Processor (ALP) in a wait state before passing the control to the operating system (OS).

19. The computer system as claimed in claim 18, wherein, upon receipt of the SIPI, said Alternate Logical Processor (ALP) executes the memory initialization and the PCI bus initialization respectively, while the Boot-Strap Logical Processor (BSLP) initializes all internal hardware of the host chipset and all storage devices connected to the host chipset, and after the memory initialization and PCI bus initialization are completed, indicates to the Boot-Strap Logical Processor (BSLP) that the memory initialization and PCI bus initialization are completed after all internal hardware of the host chipset and all storage devices connected to the host chipset are initialized by the Boot-Strap Logical Processor (BSLP).

20. The computer system as claimed in claim 19, wherein said memory initialization is executed by:

detecting a physical memory array plugged into the computer system;

programming the host chipset with the physical memory specifics, and initializing the physical memory using the host chipset;

detecting a physical memory ECC (Error Checking and Correction) Capability; and

programming the host chipset with the ECC capability, and writing zeros to the entire physical memory array in order to ensure that memory is usable for the operating system (OS).

21. The computer system as claimed in claim 19, wherein said PCI bus initialization is executed by:

scanning all possible PCI buses connected to the host chipset;

after each PCI bus is scanned, scanning and initializing all possible PCI devices connected thereto on an individual basis;

after each PCI device is scanned, initializing all possible PCI functions assigned thereto on an individual function; and

terminating the PCI bus initialization, when all the PCI buses, all the PCI devices connected to each PCI bus, and all PCI functions assigned to each PCI device are scanned and initialized.

12. A computer system, comprising:

a processor equipped to serve as multiple logical processors;

a host chipset connected to the processor;

PCI devices connected to the host chipset, via a PCI bus;

a main memory arranged to store the operating system (OS) for use by the processor; and

a flash memory arranged to store a basic input/output system (system BIOS) and other applications that may execute during boot up (start-up) before the operating system (OS) is loaded, wherein said system BIOS is configured to execute two different coordinate pre-boot tasks, including memory initialization and PCI bus initialization concurrently, on the processor which serve as multiple logical processors before passing control to the operating system (OS).

22. A computer readable medium having stored thereon a set of system basic input/output start-up “

system BIOS”

instructions configured a single physical processor equipped to serve as a Boot-Strap Logical Processor (BSLP) and an Alternate Logical Processor (ALP) which, when executed by a processor during start-up, cause the Boot-Strap Logical Processor (BSLP) and the Alternate Logical Processor (ALP) to perform;

detecting, at the Boot-Strap Logical Processor (BSLP), detecting a physical memory, programming the host chipset, detecting the presence of all logical processors and sending a SIPI (Startup Inter-Processor Interrupt) to wake up the Alternate Logical Processor (ALP);

initializing, at the Boot-Strap Logical Processor (BSLP), all internal hardware of the host chipset, all storage devices connected to the host chipset, and waiting for ALP code execution completion to place the Alternate Logical Processor (ALP) in a wait state before passing the control to the operating system (OS); and

executing, at the Alternate Logical Processor (ALP), memory initialization and PCI bus initialization respectively, while the Boot-Strap Logical Processor (BSLP) initializes all internal hardware of the host chipset and all storage devices connected to the host chipset, and after the memory initialization and PCI bus initialization are completed, indicates to the Boot-Strap Logical Processor (BSLP) that the memory initialization and PCI bus initialization are completed after all internal hardware of the host chipset and all storage devices connected to the host chipset are initialized by the Boot-Strap Logical Processor (BSLP).

23. The computer readable medium as claimed in claim 22, wherein said memory initialization is executed by the Alternate Logical Processor (ALP) by:

detecting a physical memory array plugged into the computer system;

programming the host chipset with the physical memory specifics, and initializing the physical memory using the host chipset;

detecting a physical memory ECC (Error Checking and Correction) Capability; and

programming the host chipset with the FCC capability, and writing zeros to the entire physical memory array in order to ensure that memory is usable for the operating system (OS).

24. The computer readable medium as claimed in claim 22, wherein said PCI bus initialization is executed by the Alternate Logical Processor (ALP) by:

scanning all possible PCI buses connected to the host chipset;

after each PCI bus is scanned, scanning and initializing all possible PCI devices connected thereto on an individual basis;

after each PCI device is scanned, initializing all possible PCI functions assigned thereto on an individual function; and

terminating the PCI bus initialization, when all the PCI buses, all the PCI devices connected to each PCI bus, and all PCI functions assigned to each PCI device are scanned and initialized.