Semiconductor memory device

• US 20030015757A1
• Filed: 09/28/2001
• Published: 01/23/2003
• Est. Priority Date: 07/19/2001
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohsawa, Takashi
• Granted Patent: US 6,617,651 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (15) on a first side of the channel body, and an auxiliary gate (18) on a second side of the channel body. With a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state, the MISFET has a first data state in which the majority carriers are accumulated and a second data state in which the majority carriers are emitted.

Claims

1. A semiconductor memory device having full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12), each of the MISFETs comprising:

a semiconductor layer (13) formed on the insulating film;

a source region (16) formed in the semiconductor layer;

a drain region (17) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;

a main gate (15) formed on a first side of the channel body to forms a channel in the channel body; and

an auxiliary gate (18) formed on a second side of the channel body, the second side being opposite to the first side,

wherein with a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state,

the MISFET has a first data state in which the majority carriers are accumulated in the portion of the second side of the channel body and a second data state in which the majority carriers accumulated in the portion of the second side of the channel body are emitted.

2. The semiconductor memory device according to claim 1,

wherein the first data state is set by the impact ionization generated near a drain junction with a pentode operation of the MISFET, and

the second data state is set by sending a forward bias current between the channel body and the drain region (17).

3. The semiconductor memory device according to claim 1, wherein the first side of the channel body is a top side face of the semiconductor layer (13), the second side of the channel body is a back side face of the semiconductor layer (13) and the main gate (15) is formed on the top side face via a gate insulating film (14).

4. The semiconductor memory device according to claim 3, wherein the auxiliary gate (18) is an impurity diffusion layer formed on the semiconductor substrate (11).

5. The semiconductor memory device according to claim 3, wherein the auxiliary gate (18) is an impurity doping layer (21) buried between the semiconductor substrate (11) and the insulating film (12).

6. The semiconductor memory device according to claim 3, wherein the auxiliary gate (18) is an impurity doping layer (21) buried in the insulating film (12).

7. The semiconductor memory device according to claim 3, wherein the main gates are formed in one direction to constitute a word line (WL) and the auxiliary gates are formed in parallel with the word line in the form of a stripe to constitute an impurity doping layer (21) buried in the insulating film (12).

8. The semiconductor memory device according to claim 3, wherein a pair of the auxiliary gates (22) are buried in the insulating film (12) so as to be opposite to each other, the auxiliary gates being located at both bottom side faces of the semiconductor layer (13).

9. The semiconductor memory device according to claim 1, wherein the MISFETs are arranged in the form of a matrix to constitute a cell array, the drain regions (17) are connected to bit lines (BL), the main gates (15) constitute word lines (WL) intersecting the bit lines, the source regions (16) are connected to a fixed potential line and the auxiliary gate (18) is formed as a common electrode shared among the memory cells.

10. The semiconductor memory device according to claim 9, wherein the auxiliary gate (18) is formed as the common electrode for the whole cell array.

11. The semiconductor memory device according to claim 8, wherein the MISFETs are arranged in the form of a matrix to constitute a cell array, the drain regions (17) are connected to bit lines (BL), the main gates (15) constitute word lines (WL) intersecting the bit lines, the auxiliary gates constitute plate lines (PL) in parallel with the bit lines and the source reigons (16) are connected to a fixed potential line.

12. The semiconductor memory device according to claim 1, wherein the MISFETs are arranged in the form of a matrix to constitute a cell array, the drain regions (17) are connected to bit lines (BL), the main gates (15) constitute word lines (WL) intersecting the bit lines, the source reigons (16) are connected to a fixed potential line and the auxiliary gates constitute plate lines (PL) in parallel with the bit lines, the plate lines being located between the bit lines.

13. The semiconductor memory device according to claim 1, further comprising a mimic transistor (90) which has the same structure as the MISFET in addition to the memory cells (MC), wherein voltages applied to the MISFETs are adjusted by a test using the mimic transistor.

14. The semiconductor memory device according to claim 13, wherein a main gate, an auxiliary gate, a source region and a drain region of the mimic transistor (90) are connected to test pads, respectively.

15. The semiconductor memory device according to claim 1, further comprising:

an internal voltage generating circuit (207) which generates control voltages applied to the main gate on the basis of a write operation mode, a read operation mode or a holding operation mode and a fixed voltage applied to the auxiliary gate during a memory operation;

a nonvolatile memory circuit (208) capable of programming values of the control voltages and the fixed voltage on the basis of a test result; and

an initial setting resistor (209) which reads the values from the nonvolatile memory circuit to hold them and controls voltages of the control voltages and the fixed voltage of the internal voltage generating circuit.

16. The semiconductor memory device according to claim 15, further comprising a mimic transistor (90) which has the same structure as the MISFET in addition to the memory cells (MC), wherein a main gate, an auxiliary gate, a source region and a drain region of the mimic transistor (90) are connected to test pads, respectively.

18. The semiconductor memory device according to claim 17,

wherein the first data state is set by the impact ionization generated near a drain junction with a pentode operation of the MISFET, and

the second data state is set by sending a forward bias current between the channel body and the drain region (34).

19. The semiconductor memory device according to claim 17, wherein the source region (32) is formed in the bottom portion of the pillar semiconductor portion and shared among the memory cells.

20. The semiconductor memory device according to claim 19, wherein the source region (32) is shared among all the memory cells in a cell array.

21. The semiconductor memory device according to claim 17, wherein the MISFETs are arranged in the form of a matrix to constitute a cell array, the drain regions (34) are connected to bit lines (BL), the main gates (36) constitute word lines (WL), the auxiliary gates (38) constitute plate lines (PL) and the source regions (32) are connected to a fixed potential line.

22. The semiconductor memory device according to claim 17, further comprising a mimic transistor (90) which has the same structure as the MISFET in addition to the memory cells (MC), wherein voltages applied to the MISFET are adjusted by a test using the mimic transistor.

23. The semiconductor memory device according to claim 22, wherein a main gate, an auxiliary gate, a source region and a drain region of the mimic transistor (90) are connected to test pads, respectively.

24. The semiconductor memory device according to claim 17, further comprising:

an internal voltage generating circuit (207) which generates control voltages applied to the main gate on the basis of a write operation mode, a read operation mode or a holding operation mode and a fixed voltage applied to the auxiliary gate during a memory operation;

a nonvolatile memory circuit (208) capable of programming values of the control voltages and the fixed voltage on the basis of a test result; and

an initial setting resistor (209) which reads the values from the nonvolatile memory circuit to hold them and controls voltages of the control voltages and the fixed voltage of the internal voltage generating circuit.

25. The semiconductor memory device according to claim 24, further comprising a mimic transistor (90) which has the same structure as the MISFET in addition to the memory cells (MC), wherein a main gate, an auxiliary gate, a source region and a drain region of the mimic transistor (90) are connected to test pads, respectively.

17. A semiconductor memory device having full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (31), each of the MISFETs comprising:

a pillar semiconductor portion (33) formed on the semiconductor substrate in the form of a pillar shape;

a source region (32) formed in one of a top portion and a bottom portion of the pillar semiconductor portion;

a drain region (34) formed in the other of the top portion and the bottom portion of the pillar semiconductor portion and formed apart from the source region, the pillar semiconductor portion between the source region and the drain region serving as a channel body in a floating state;

a main gate (36) formed on a first vertical face of the channel body to forms a channel in the channel body; and

an auxiliary gate (38) formed on a second vertical face of the channel body, the second vertical face being opposite to the first vertical face,

wherein with a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state,

the MISFET has a first data state in which the majority carriers are accumulated in the portion of the second vertical face of the channel body and a second data state in which the majority carriers accumulated in the portion of the second vertical face of the channel body are emitted.