Semiconductor memory device

• US 6,617,651 B2
• Filed: 09/28/2001
• Issued: 09/09/2003
• Est. Priority Date: 07/19/2001
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohsawa, Takashi
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US09/964,851
• Publication Number:
  US 20030015757A1
• Time in Patent Office: 711 Days
• Field of Search: 257/365, 257/366
• US Class Current: 257/366
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (15) on a first side of the channel body, and an auxiliary gate (18) on a second side of the channel body. With a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state, the MISFET has a first data state in which the majority carriers are accumulated and a second data state in which the majority carriers are emitted.

Claims

1. A semiconductor memory device

a semiconductor substrate;

and

memory cells formed on the semiconductor substrate via an insulating film, each of the memory cells being a unit for storing one bit data and each of the memory cells consisting of one full depletion type MISFET, wherein each of the memory cells comprises;

a semiconductor layer formed on the insulating film;

a source region formed in the semiconductor layer;

a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;

a main gate formed on a first side of the channel body to form a channel in the channel body; and

an auxiliary gate formed on a second side of the channel body, the second side being opposite to the first side,

wherein the MISFET has a first data state in which the majority carriers are accumulated in a portion of the second side of the channel body and a second data state in which the majority carriers accumulated in the portion of the second side of the channel body are emitted.

2. The semiconductor memory device according to claim 1,

wherein the first data state is set by the impact ionization generated near a drain junction with a pentode operation of the MISFET, and

the second data state is set by sending a forward bias current between the channel body and the drain region.

3. The semiconductor memory device according to claim 1, wherein the first side of the channel body is a top side face of the semiconductor layer, the second side of the channel body is a back side face of the semiconductor layer and the main gate is formed on a top side face via a gate insulating film.

4. The semiconductor memory device according to claim 3, wherein the auxiliary gate is an impurity diffusion layer formed on the semiconductor substrate.

5. The semiconductor memory device according to claim 3, wherein the auxiliary gate is an impurity doping layer buried between the semiconductor substrate and the insulating film.

6. A semiconductor memory device having full depletion type MISFETs to constitute memory cells on a semiconductor substrate via an insulating film, each of the MISFETs comprising:

a semiconductor layer formed on the insulating film;

a source region formed in the semiconductor layer;

a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;

a main gate formed on a first side of the channel body to form a channel in the channel body; and

an auxiliary gate formed on a second side of the channel body, the second side being opposite to the first side, the auxiliary gate being connected to an auxiliary gate terminal to which a constant voltage is applied,

wherein the MISFET has a first data state in which the majority carriers are accumulated in a portion of the second side of the channel body and a second data state in which the majority carriers accumulated in the portion of the second side of the channel body are emitted.

7. The semiconductor memory device according to claim 6, wherein the first data state is set by the impact ionization generated near a drain junction with a pentode operation of the MISFET, and the second data state is set by sending a forward bias current between the channel body and the drain region.

8. The semiconductor memory device according to claim 6, wherein the first side of the channel body is a top side face of the semiconductor layer, the second side of the channel body is a back side face of the semiconductor layer and the main gate is formed on a top side face via a gate insulating film.

9. The semiconductor memory device according to claim 8, wherein the auxiliary gate is an impurity diffusion layer formed on the semiconductor substrate.

10. The semiconductor memory device according to claim 8, wherein the auxiliary gate is an impurity doping layer buried between the semiconductor substrate and the insulating film.