Structure and method for fabricating an integrated phased array circuit

• US 20030022395A1
• Filed: 05/02/2002
• Published: 01/30/2003
• Est. Priority Date: 07/17/2001
• Status: Abandoned Application

• Current Assignee: Thoughtbeam, Inc.
• Original Assignee: Thoughtbeam, Inc.
• Inventors: Olds, Keith A.
• Application Number:
  US10/136,324
• Publication Number:
  US 20030022395A1
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV

Abstract

Phased array components utilizing two or more different types of semiconductor in one monolithic device are provided. High quality epitaxil layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxil growth of single crystal silicon onto single crystal oxidematerials. A monolithic phased array system (604) is formed including digitizer (626) formed on compound semiconductor material (614) as well as processors (620, 628, 632) formed on silicon (616). The processors may be networked (622) to form a distributed computing system (604) creating a complete wafer-scale system (600) that includes signal processing and application functions.

Claims

1. A monolithic device comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material; and

a first phased array component formed in at least one of the monocrystalline silicon substrate, the amorphous oxide material, the monocrystalline perovskite oxide material and the monocrystalline compound semiconductor material.

2. The structure of claim 1 wherein the first phased array component is formed in the monocrystalline silicon substrate.

3. The structure of claim 1 wherein the first phased array component is formed in the monocrystalline compound semiconductor material.

4. The structure of claim 3 wherein a second phased array component is formed in the monocrystalline silicon substrate.

5. The structure of claim 1 wherein the first phased array component comprises an application specific integrated circuit.

6. The structure of claim 1 wherein the first phased array component comprises a phase shifter.

7. The structure of claim 1 wherein the first phased array component comprises an amplifier.

8. The structure of claim 4 wherein the first phased array component comprises a first transistor and the second phased array component comprises a second transistor.

9. The structure of claim 4 wherein the first phased array component comprises a low noise amplifier and the second phased array component comprises an application specific integrated circuit.

10. The structure of claim 4 further comprising a mixer formed in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

11. The structure of claim 4 further comprising a voltage controlled oscillator formed in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

12. The structure of claim 4 further comprising a switch formed in the monocrystalline silicon substrate.

13. The structure of claim 4 wherein the first phased array component comprises a low noise amplifier and the second phased array component comprises a transistor;

further comprising a phase shifter component formed in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

14. The structure of claim 4 wherein the second phased array component comprises a control transistor and the first phased array component comprises one of a phase shifter and an amplifier transistor.

16. The structure of claim 1 wherein the first phased array component comprises a transmit path operable to be connected with an antenna and a distribution network.

17. The structure of claim 1 wherein the first phased array component comprises a transceiver having at least one switch operatively connectable with transmit and receive paths.

15. The structure of claim I wherein the first phased array component comprises a receive path operable to be connected with an antenna and a distribution network.

18. The structure of claim I wherein the first phased array component comprises one phased array cell operatively connected with an antenna and a distribution network and further comprising a plurality of additional phased array cells operatively connected with a respective plurality of additional antennae and the distribution network, the plurality of additional phased array cells formed in at least one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

19. A process for fabricating a monolithic device comprising:

(a) providing a monocrystalline silicon substrate;

(b) depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness that would result in strain-induced defects;

(c) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;

(d) epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film; and

(e) forming a first phased array component in one of the monocrystalline silicon substrate, the amorphous oxide material, the monocrystalline perovskite oxide material and the monocrystalline compound semiconductor material.

20. The process of claim 19 wherein (e) comprises forming the first phased array component in the monocrystalline silicon substrate.

21. The process of claim 19 wherein (e) comprises forming the first phased array component in the monocrystalline compound semiconductor material.

22. The process of claim 21 further comprising:

(f) forming a second phased array component in the monocrystalline silicon substrate.

23. The process of claim 19 wherein (e) comprises forming an application specific integrated circuit.

24. The process of claim 19 wherein (e) comprises forming a phase shifter.

25. The process of claim 19 wherein (e) comprises forming an amplifier.

26. The process of claim 22 wherein (e) comprises forming a first transistor and (f) comprises forming a second transistor.

27. The process of claim 22 wherein (e) comprises forming a low noise amplifier and (f) comprises forming an application specific integrated circuit.

28. The process of claim 22 further comprising:

(g) forming a mixer in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

29. The process of claim 22 further comprising:

(g) forming a voltage controlled oscillator in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

30. The process of claim 22 further comprising:

(g) forming a switch in the monocrystalline silicon substrate.

31. The process of claim 22 wherein (e) comprises forming a low noise amplifier and (f) comprises forming a transistor;

further comprising;

(g) forming a phase shifter component in one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

32. The process of claim 22 wherein (f) comprises forming a control transistor and (e) comprises forming one of a phase shifter and an amplifier transistor.

33. The process of claim 19 wherein (e) comprises forming a receive path operable to be connected with an antenna and a distribution network.

34. The process of claim 19 wherein (e) comprises forming a transmit path operable to be connected with an antenna and a distribution network.

35. The process of claim 19 wherein (e) comprises forming a transceiver having at least one switch operatively connectable with transmit and receive paths.

36. The process of claim 19 wherein (e) comprises forming one phased array cell operatively connectable with an antenna and a distribution network;

and

further comprising;

(f) forming a plurality of additional phased array cells operatively connectable with a respective plurality of additional antennae and the distribution network, the plurality of additional phased array cells formed in at least one of the monocrystalline silicon substrate and the monocrystalline compound semiconductor material.

37. A monolithic device comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a set of phased array element cells formed in the monocrystalline compound semiconductor material; and

a digital beamformer carried by the monocrystalline silicon substrate and coupled with the set of phased array element cells.

38. The device of claim 37 wherein each phased array element cell comprises a respective array element, a respective A/D converter, and a respective D/A converter.

39. The device of claim 37 wherein the digital beamformer is formed in a region of monocrystalline silicon carried by the monocrystalline silicon substrate.

40. The device of claim 37 wherein the monocrystalline silicon substrate comprises an entire wafer of monocrystalline silicon.

41. The device of claim 40 wherein the set of phased array element cells is distributed over an area of the wafer of at least 150 cm².

42. The device of claim 37 wherein each phased array element cell comprises a respective element processor, and wherein the digital beamformer is included in a supervisory processor carried by the monocrystalline silicon substrate.

43. The device of claim 42 wherein each element processor comprises a respective transmit processor, a respective receive processor, and a respective distributed processor.

44. The device of claim 43 wherein the supervisory processor comprises the digital beamformer and a resource/process manager, said resource/process manager cooperating with the distributed processors to form a distributed computing system.

45. The device of claim 44 wherein the supervisory processor further comprises a personality controller operative to select any one of a plurality of personalities for execution by the supervisory processor and the element processors.

46. The device of claim 45 wherein the plurality of personalities comprises a first personality that configures the phased array element cells for communication and a second personality that configures the phased array element cells for reflection sensing.

47. A monolithic device comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a set of phased array element cells formed in the monocrystalline compound semiconductor material, each element cell comprising a respective element processor; and

a supervisory processor carried by the monocrystalline silicon substrate and coupled with the element processors.

48. The device of claim 47 wherein each phased array element cell comprises a respective phased array element, a respective A/D converter, and a respective D/A converter.

49. The device of claim 47 wherein the supervisory processor is formed in a region of monocrystalline silicon carried by the monocrystalline silicon substrate.

50. The device of claim 47 wherein the monocrystalline silicon substrate comprises an entire wafer of monocrystalline silicon.

51. The device of claim 50 wherein the set of phased array element cells is distributed over an area of the wafer of at least 150 cm².

52. The device of claim 47 wherein the supervisory processor cooperates with the element processors to form a distributed computing system.

53. The device of claim 52 wherein the supervisory processor further comprises a personality controller operative to select any one of a plurality of personalities for execution by the supervisory processor and the element processors.

54. The device of claim 53 wherein the plurality of personalities comprises a first personality that configures the phased array element cells for communication and a second personality that configures the phased array element cells for reflection sensing.

55. A process for fabricating a monolithic device comprising:

(a) providing a monocrystalline silicon substrate;

(b) depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness that would result in strain-induced defects;

(c) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;

(d) epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film;

(e) forming a set of phased array element cells in the monocrystalline compound semiconductor material; and

(f) forming a digital beamformer carried by the monocrystalline silicon substrate and coupled with the set of phased array element cells.

56. The process of claim 55 wherein each phased array element cell formed in (e) comprises a respective phased array element, a respective A/D converter, and a respective D/A converter.

57. The process of claim 55 wherein the digital beamformer is formed in (f) in a region of monocrystalline silicon carried by the monocrystalline silicon substrate.

58. The process of claim 55 wherein the monocrystalline silicon substrate provided in (a) comprises an entire wafer of monocrystalline silicon.

59. The process of claim 58 wherein the set of phased array element cells is distributed in (e) over an area of the wafer of at least 150 cm².

60. The process of claim 55 wherein each phased array element cell formed in (e) comprises a respective element processor, and wherein the digital beamformer formed in (f) is included in a supervisory processor carried by the monocrystalline silicon substrate.

61. The process of claim 60 wherein each element processor comprises a respective transmit processor, a respective receive processor, and a respective distributed processor.

62. The process of claim 61 wherein the supervisory processor comprises a resource/process manager, said resource/process manager cooperating with the distributed processors to form a distributed computing system.

63. The process of claim 62 wherein the supervisory processor further comprises a personality controller operative to select any one of a plurality of personalities for execution by the supervisory processor and the element processors.

64. The process of claim 63 wherein the plurality of personalities comprises a first personality that configures the phased array element cells for communication and a second personality that configures the phased array element cells for reflection sensing.

65. A process for fabricating a monolithic device comprising:

(a) providing a monocrystalline silicon substrate;

(b) depositing a monocrystalline perovskite oxide film overlying the monocrystalline silicon substrate, the film having a thickness less than a thickness that would result in strain-induced defects;

(c) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide film and the monocrystalline silicon substrate;

(d) epitaxially forming a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide film;

(e) forming a set of phased array element cells in the monocrystalline compound semiconductor material, each element cell comprising a respective element processor; and

(f) forming a supervisory processor carried by the monocrystalline silicon substrate and coupled with the element processors.

66. The process of claim 65 wherein each phased array element cell formed in (e) comprises a respective phased array element, a respective A/D converter, and a respective D/A converter.

67. The process of claim 65 wherein the supervisory processor is formed in (f) in a region of monocrystalline silicon carried by the monocrystalline silicon substrate.

68. The process of claim 65 wherein the monocrystalline silicon substrate comprises an entire wafer of monocrystalline silicon.

69. The process of claim 68 wherein the set of phased array element cells is distributed in (e) over an area of the wafer of at least 150 cm².

70. The process of claim 65 wherein the supervisory processor cooperates with the element processors to form a distributed computing system.

71. The process of claim 70 wherein the supervisory processor further comprises a personality controller operative to select any one of a plurality of personalities for execution by the supervisory processor and the element processors.

72. The process of claim 71 wherein the plurality of personalities comprises a first personality that configures the phased array element cells for communication and a second personality that configures the phased array element cells for reflection sensing.