Bumping technology in stacked die configurations
First Claim
1. A stacked semiconductor assembly, comprising:
- a first semiconductor die including an active surface and a backside, said active surface including a plurality of bond pads and at least one redistribution bond pad circuit thereon, said plurality of bond pads electrically connected to integrated circuitry of said first semiconductor die, said at least one redistribution bond pad circuit independent from the integrated circuitry of said first semiconductor die and including a plurality of redistribution bond pads;
a second semiconductor die including an active surface, a backside, and a plurality of bond pads on said active surface, said active surface of said second semiconductor die facing said active surface of said first semiconductor die; and
at least one electrical connector extending between at least one bond pad of said plurality of bond pads on said active surface of said second semiconductor die and at least one redistribution bond pad of said plurality of redistribution bond pads on said first semiconductor die.
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Accused Products
Abstract
A stacked semiconductor package, and a method of forming the same, including a plurality of stacked semiconductor devices on a substrate. The semiconductor devices are stacked in an active surface to backside configuration. The top semiconductor die is flipped over to face and the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on the top semiconductor die to a bond pad on a substrate.
45 Citations
97 Claims
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1. A stacked semiconductor assembly, comprising:
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a first semiconductor die including an active surface and a backside, said active surface including a plurality of bond pads and at least one redistribution bond pad circuit thereon, said plurality of bond pads electrically connected to integrated circuitry of said first semiconductor die, said at least one redistribution bond pad circuit independent from the integrated circuitry of said first semiconductor die and including a plurality of redistribution bond pads;
a second semiconductor die including an active surface, a backside, and a plurality of bond pads on said active surface, said active surface of said second semiconductor die facing said active surface of said first semiconductor die; and
at least one electrical connector extending between at least one bond pad of said plurality of bond pads on said active surface of said second semiconductor die and at least one redistribution bond pad of said plurality of redistribution bond pads on said first semiconductor die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor assembly, comprising:
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a substrate;
a first semiconductor die including an active surface, a second surface, and a plurality of peripheral edges, said second surface disposed on said substrate, said active surface having a plurality of bond pads thereon;
a second semiconductor die including an active surface, a second surface, a plurality of peripheral edges and a plurality of bond pads on said active surface, said active surface of said second semiconductor die facing said active surface of said first semiconductor die, at least one edge of said plurality of peripheral edges of said second semiconductor die extending laterally beyond at least one corresponding peripheral edge of said plurality of peripheral edges of said first semiconductor die; and
at least one connective element extending from at least one bond pad of said plurality of bond pads on of said second semiconductor die to a corresponding contact area of said substrate adjacent to said at least one corresponding peripheral edge of said first semiconductor die. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A method of forming a stacked semiconductor assembly, comprising:
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providing a first semiconductor die including an active surface and a backside, said active surface including integrated circuitry, a plurality of bond pads, a plurality of redistribution pads and a plurality of metal traces thereon, said plurality of redistribution pads independent from said integrated circuitry, at least one metal trace of said plurality of metal traces connecting at least a first redistribution pad of said plurality of redistribution pads and at least a second redistribution pad of said plurality of redistribution pads;
providing a second semiconductor die including an active surface and a backside, said active surface of said first semiconductor die facing said active surface of said second semiconductor die, said active surface of said second semiconductor die including a plurality of bond pads thereon;
electrically connecting said first redistribution pad of said first semiconductor die and a corresponding bond pad of said plurality of bond pads of said second semiconductor die; and
electrically connecting said second redistribution pad of said first semiconductor die and a corresponding contact area of a substrate. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44)
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45. A method of forming a stacked semiconductor package, comprising:
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providing a substrate including a plurality of contact areas;
providing a first semiconductor die including an active surface, a backside, and a plurality of peripheral edges, said backside second surface disposed above said substrate, said active surface including a plurality of bond pads thereon;
disposing a top semiconductor die above said first semiconductor die, said top semiconductor die including an active surface, a backside and a plurality of peripheral edges, said active surface of said top semiconductor die facing said active surface of said first semiconductor die and including a plurality of bond pads thereon, at least one edge of said plurality of peripheral edges of said top semiconductor die extending laterally beyond at least one corresponding peripheral edge of said plurality of peripheral edges of said first semiconductor die; and
extending at least one conductive element between at least one bond pad of said plurality of bond pads on said top semiconductor die and to a corresponding contact area of said substrate adjacent to said at least one corresponding peripheral edge of said first semiconductor die. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A method of designing a semiconductor device to be used as a lower semiconductor device in a stacked semiconductor assembly, said method comprising:
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providing a first semiconductor device including an active surface and a backside, said active surface including integrated circuitry and a plurality of bond pads thereon; and
designing at least one redistribution circuit on said active surface, said redistribution circuit independent from said integrated circuitry. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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76. A semiconductor device for use in a stacked semiconductor assembly, said semiconductor device comprising:
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a backside;
an active surface including a plurality of bond pads; and
at least one redistribution bond pad circuit on said active surface, said at least one redistribution bond pad circuit independent from integrated circuitry of said semiconductor device. - View Dependent Claims (77, 78, 79, 80, 81, 82, 83, 84, 85, 86)
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87. A method for redistributing bond pads of a semiconductor device, said method comprising:
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providing a semiconductor device including an active surface having a first set substantially centrally located bond pads and a second set of substantially peripherally located bond pads thereon, said second set of substantially peripherally located bond pads and said first set substantially centrally located bond pads electrically independent from said semiconductor device; and
electrically connecting at least one bond pad of said first set of substantially centrally located bond pads to a corresponding second bond pad of said second set of peripherally located bond pads. - View Dependent Claims (88, 89, 90, 91, 92, 93, 94, 95, 96, 97)
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Specification