Field effect transistor switch circuit

• US 20030116780A1
• Filed: 12/19/2002
• Published: 06/26/2003
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Suwa, Atsushi, Nakatsuka, Tadayoshi, Tara, Katsushi, Komatsu, Tadashi
• Granted Patent: US 7,138,846 B2
• Time in Patent Office: Days
• US Class Current: 257/130
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

In order that the DC potential of the input terminal does not rise, whereby ON/OFF switching is accordingly performed normally, even when a signal having a large amplitude is inputted to an input terminal, thereby the depletion layer expands due to electron trapping effect, a first field effect transistor is connected between a first switch input terminal and a first switch output terminal in a manner that the source is arranged on the first switch input terminal side, a second field effect transistor is connected between the first switch output terminal and a second switch input terminal in a manner that the source is arranged on the second switch input terminal side, a third field effect transistor is connected between the second switch input terminal and a second switch output terminal in a manner that the source is arranged on the second switch input terminal side, and a fourth field effect transistor is connected between the second switch output terminal and the first switch input terminal in a manner that the source is arranged on the first switch input terminal side. Further, each of first through fourth resistors is connected between the gate and the source of each of the first through fourth field effect transistors.

Claims

1. A field effect transistor switch circuit comprising:

first, second, and third switch terminals;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said third switch terminal;

a first resistor connected between the control electrode and any one of a pair of said main electrodes of said first field effect transistor; and

a second resistor connected between the control electrode and any one of a pair of said main electrodes of said second field effect transistor.

2. A field effect transistor switch circuit according to claim 1, wherein each of said first and second field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

7. A field effect transistor switch circuit according to claim 1, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

8. A field effect transistor switch circuit according to claim 2, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

13. A field effect transistor switch circuit according to claim 7, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

14. A field effect transistor switch circuit according to claim 8, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

3. A field effect transistor switch circuit comprising:

first and second switch terminals;

a ground terminal;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said ground terminal;

a first resistor connected between the control electrode and any one of a pair of said main electrodes of said first field effect transistor; and

a second resistor connected between the control electrode and any one of a pair of said main electrodes of said second field effect transistor.

4. A field effect transistor switch circuit according to claim 3, wherein each of said first and second field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

9. A field effect transistor switch circuit according to claim 3, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

10. A field effect transistor switch circuit according to claim 4, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

15. A field effect transistor switch circuit according to claim 9, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

16. A field effect transistor switch circuit according to claim 10, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

5. A field effect transistor switch circuit comprising:

first, second, third, and fourth switch terminals;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said second switch terminal and said third switch terminal;

a third field effect transistor a pair of the main electrodes of which are connected respectively to said third switch terminal and said fourth switch terminal;

a fourth field effect transistor a pair of the main electrodes of which are connected respectively to said fourth switch terminal and said first switch terminal;

a first resistor connected between the control electrode and any one of a pair of said main electrodes of said first field effect transistor;

a second resistor connected between the control electrode and any one of a pair of said main electrodes of said second field effect transistor;

a third resistor connected between the control electrode and any one of a pair of said main electrodes of said third field effect transistor; and

a fourth resistor connected between the control electrode and any one of a pair of said main electrodes of said fourth field effect transistor.

6. A field effect transistor switch circuit according to claim 5, wherein each of said first, second, third, and fourth field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

11. A field effect transistor switch circuit according to claim 5, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

12. A field effect transistor switch circuit according to claim 6, wherein a correction capacitance for correcting unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said field effect transistor during the OFF state of said field effect transistor is provided between the control electrode and any one of a pair of the main electrodes of said field effect transistor.

17. A field effect transistor switch circuit according to claim 11, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

18. A field effect transistor switch circuit according to claim 12, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

19. Afield effect transistor switch circuit comprising:

first, second, and third switch terminals;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said third switch terminal;

a first correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said first field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said first field effect transistor during the OFF state of said first field effect transistor; and

a second correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said second field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said second field effect transistor during the OFF state of said second field effect transistor.

20. A field effect transistor switch circuit according to claim 19, wherein each of said first and second field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

25. A field effect transistor switch circuit according to claim 19, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

26. A field effect transistor switch circuit according to claim 20, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

21. A field effect transistor switch circuit comprising:

first and second switch terminals;

a ground terminal;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said ground terminal;

a first correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said first field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said first field effect transistor during the OFF state of said first field effect transistor; and

a second correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said second field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said second field effect transistor during the OFF state of said second field effect transistor.

22. A field effect transistor switch circuit according to claim 21, wherein each of said first and second field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

27. A field effect transistor switch circuit according to claim 21, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

28. A field effect transistor switch circuit according to claim 22, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

23. A field effect transistor switch circuit comprising:

first, second, third, and fourth switch terminals;

a first field effect transistor a pair of the main electrodes of which are connected respectively to said first switch terminal and said second switch terminal;

a second field effect transistor a pair of the main electrodes of which are connected respectively to said second switch terminal and said third switch terminal;

a third field effect transistor a pair of the main electrodes of which are connected respectively to said third switch terminal and said fourth switch terminal;

a fourth field effect transistor a pair of the main electrodes of which are connected respectively to said fourth switch terminal and said first switch terminal;

a first correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said first field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said first field effect transistor during the OFF state of said first field effect transistor;

a second correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said second field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said second field effect transistor during the OFF state of said second field effect transistor;

a third correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said third field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said third field effect transistor during the OFF state of said third field effect transistor; and

a fourth correction capacitance which is connected between the control electrode and any one of a pair of the main electrodes of said fourth field effect transistor and thereby corrects unbalance of equivalent capacitances between the control electrode and each of a pair of the main electrodes of said fourth field effect transistor during the OFF state of said fourth field effect transistor.

24. A field effect transistor switch circuit according to claim 23, wherein each of said first, second, third, and fourth field effect transistors is composed of a serial circuit of a plurality of field effect transistors.

29. A field effect transistor switch circuit according to claim 23, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.

30. A field effect transistor switch circuit according to claim 24, wherein said correction capacitance is smaller than the depletion layer capacitance during the ON-state of said field effect transistor, and larger than the depletion layer capacitance during the OFF-state.