Method to improve STI nano gap fill and moat nitride pull back

• US 20030181022A1
• Filed: 02/28/2003
• Published: 09/25/2003
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mehrad, Freidoon, Mansoori, Majid M., Chen, Zhihao
• Granted Patent: US 6,828,213 B2
• Time in Patent Office: Days
• US Class Current: 438/437
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Abstract

A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

Claims

1. A method to provide a more uniform STI oxide liner and also make the moat nitride pullback possible comprising the steps of:

depositing and etching a nitride liner to form a thin side wall nitride formation in shallow trench isolation before STI liner oxidation.

2. A method to provide a more uniform STI oxide liner comprising the steps of:

depositing and etching a nitride liner to form a thin side wall nitride formation in shallow trench isolation before STI liner oxidation.

3. A method to provide the moat nitride pullback possible comprising the steps of:

depositing and etching a nitride liner to form a thin side wall nitride formation in shallow trench isolation before STI gap fill.

4. A method of STI formation on a silicon wafer comprising the steps of:

growing pad oxide on the face of the silicon wafer;

deposit nitride layer on said pad oxide;

moat patterning, moat etching and moat etch cleaning;

growing thermal oxide;

etching a part of the moat nitride using hot phosphoric acid;

depositing a very thin nitride liner;

etching the nitride to form a thin side wall nitride in the STI trench;

performing Hydroflouric (HF) acid deglaze process; and

performing STI liner oxidation.

5. The method of claim 4 including the step of depositing oxide to fill the STI trenches.

6. The method of claim 5 including the steps of CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP;

moat nitride etch;

growing dummy oxide, HF deglazing, growing HV gate, HF deglaze and grow LV gate oxide; and

depositing polysilicon and forming the transistor gates.

7. The method of claim 4 wherein the growing thermal oxide grows 20-40 Anstroms.

8. The method of claim 4 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms.

9. A method of STI formation on a silicon wafer comprising the steps of:

growing pad oxide on the face of the silicon wafer;

deposit nitride layer on said pad oxide;

moat patterning, moat etching and moat etch cleaning;

growing thermal oxide;

etching a part of the moat nitride;

depositing a very thin nitride liner;

etching the nitride to form a thin side wall nitride in the STI trench;

deglazing for under cut and moat pad oxide deglaze; and

performing STI liner oxidation.

10. The method of claim 9 wherein the growing thermal oxide grows 20-40 Anstroms.

11. The method of claim 9 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms