Method to improve STI nano gap fill and moat nitride pull back

• US 6,828,213 B2
• Filed: 02/28/2003
• Issued: 12/07/2004
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mehrad, Freidoon, Mansoori, Majid M., Chen, Zhihao
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/376,021
• Publication Number:
  US 20030181022A1
• Time in Patent Office: 648 Days
• Field of Search: 438/424, 438/435, 438/700, 438/443
• US Class Current: 438/435
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Abstract

A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

Claims

1. A method of STI formation on a silicon wafer comprising the steps of:

growing pad oxide on the face of the silicon wafer;

deposit nitride layer on said pad oxide;

moat patterning, moat etching and moat etch cleaning;

growing thermal oxide;

etching a part of the moat nitride layer using hot phosphoric acid;

depositing a very thin nitride liner;

dry plasma etching the thin nitride liner to form a thin side wall nitride in the STI trench separated from the moat nitride layer such that during subsequent moat nitride wet etch the side wall nitride in the STI trench will not be affected;

performing Hydrofluoric (HF) acid deglaze process; and

performing STI liner oxidation.

2. The method of claim 1 including the step of depositing oxide to fill the STI trenches.

3. The method of claim 2 including the steps of CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP;

moat nitride etch;

growing dummy oxide;

HF deglazing, growing HV gate, HF deglaze and grow LV gate oxide; and

depositing polysilicon and forming the transistor gates.

4. The method of claim 1 wherein the growing thermal oxide grows 20-40 Angstroms.

5. The method of claim 1 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms.

6. The method of STI formation on a silicon wafer comprising the steps of:

growing pad oxide on the face of the silicon wafer;

deposit nitride layer on said pad oxide;

moat patterning, moat etching and moat etch cleaning;

growing thermal oxide;

etching a part of the moat nitride layer;

depositing a very thin nitride liner;

dry plasma etching the thin nitride liner to form a thin side wall nitride in the STI trench separated from the moat nitride layer such that during subsequent moat nitride wet etch the side wall nitride in the STI trench will not be affected;

deglazing for under cut and moat pad oxide deglaze; and

performing STI liner oxidation;

depositing oxide to fill the STI trenches;

CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP; and

performing moat nitride wet etch.

7. The method of claim 6 wherein the growing thermal oxide grows 20-40 Angstroms.

8. The method of claim 6 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms.

9. The method of claim 6 further including the step of:

growing dummy oxide;

HF deglazing, growing HV gate, HF deglaze and grow LV gate oxide; and

depositing polysilicon and forming the transistor gates.