Communications architecture for a high throughput storage processor employing extensive I/O parallelization

• US 20030188099A1
• Filed: 03/29/2002
• Published: 10/02/2003
• Est. Priority Date: 03/29/2002
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Baxter, William H. III
• Granted Patent: US 6,813,689 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 2211/1016 Continuous RAID, i.e. RAID system that allows streaming or continuous media, e.g. VOD
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A storage processor for a block storage RAID array services disk storage block requests from one or more hosts. At its heart, a application specific integrated chip (ASIC) supports a store and forward data transfer regime in that host to disk transfers are made by placing data in storage processor memory under control of the storage processor, operated on by the ASIC, and sent to the disk array. Efficient handling of ordering is, preferably, provided by hardware logic-based masking of interrupts and by other mechanisms. Embodiments help to insure that shared data paths are flushed of non-critical data quickly to sustain more critical data, for example, that required to sustain high throughput.

Claims

1. A storage processor for a RAID system, comprising:

a communications device connecting at least a front end (FE) connectable to a requesting device, a back end (BE) connectable to a disk array, and a control processor and control memory;

said communications device connecting a memory, a DMA engine, a data translator, and a crossbar switch;

at least one of said data channels including at least one buffer;

said processor initiating a process on target data transmitted, on a target data channel defined by said communications device, to said memory by said requesting device and in response to a command from said requesting device and an interrupt invoked by said requesting device;

said communications device being configured such that said processor does not respond to said interrupt until all of said target data is received in said memory.

2. A storage processor as in claim 1, wherein said communications device is configured to mask said interrupt in response to a detection thereof.

4. A storage processor as in claim 1, wherein said communications device is configured such that said processor is responsive to said interrupt and a detection of a flushing of said target data from said target channel.

5. A storage processor as in claim 4, wherein said communications device is configured to detect said flushing responsively to a buffer write pointer saved responsively to a timing of said interrupt.

6. A storage processor as in claim 1, wherein said processor is prevented from responding to said interrupt responsively to a state of a buffer in said target data channel.

3. A storage processor as in claim 3, wherein said communications device is configured to unmask said interrupt in response to a detection of a flushing of a target data channel of said target data, whereby said target data is confirmed to be received in said memory.

7. A storage processor for a RAID system, comprising:

a communications device connecting at least a front end (FE) connectable to a requesting device, a back end (BE) connectable to a disk array, and a control processor and control memory;

said communications device connecting a memory, a DMA engine, a data translator, and a crossbar switch;

at least one of said data channels including at least one buffer;

said processor initiating a process by said DMA engine, on target data transmitted on a target data channel defined by said communications device, said process requiring that said target data channel be flushed of said target data;

said processor initiating said process responsively to an interrupt invoked by said requesting device;

said communications device being configured to mask said interrupt until said target data is flushed from said target data channel.

8. A storage processor as in claim 7, wherein said communications device is configured to mask said interrupt in response to a detection thereof.

9. A storage processor as in claim 8, wherein said target data leads to said memory and said communications device is configured to unmask said interrupt in response to a detection of a flushing of a target data channel of said target data, whereby said target data is confirmed to be received in said memory.

10. A storage processor as in claim 7, wherein said communications device is configured such that said processor is responsive to said interrupt and a detection of a flushing of said target data from said target channel.

11. A storage processor as in claim 10, wherein said communications device is configured to detect said flushing responsively to a buffer write pointer saved responsively to a timing of said interrupt.

12. A storage processor as in claim 7, wherein said processor is prevented from responding to said interrupt responsively to a state of a buffer in said target data channel.

13. A method of ordering parallel I/O in a storage processor, comprising the steps of:

generating a target data transfer request;

posting target data on a target channel;

generating an interrupt applied to a controller to initiate an operation responsive to said target data;

masking said interrupt responsively to said target data being flushed from said target channel;

unmasking said interrupt responsively to said target data being cleared from said target channel.

14. A method as in claim 13, wherein said target data is user data and said target channel receives data and transfers it to a memory.

15. A method as in claim 13, wherein said step of unmasking includes detecting the state of at least one buffer in said target channel.

16. A method as in claim 15, wherein said target data is user data and said target channel receives data and transfers it to a memory.