Wiring design method of integrated circuit device, system thereof, and program product thereof

• US 20030227032A1
• Filed: 02/11/2003
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoneda, Takashi, Hosono, Toshikatsu, Nawa, Takanori
• Application Number:
  US10/361,679
• Publication Number:
  US 20030227032A1
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

An object of this invention is to provide a wiring design method of integrated circuit device capable of determining a layout without such a problem as congestion of wirings efficiently upon determination of the wiring layout in the integrated circuit device, system thereof and program product thereof. In the wiring design method for determining the route of wiring between a cell and another cell in the integrated circuit device, first, a region in which wirings are to be placed is divided vertically and horizontally (S102). Which divided regions each wiring should cross is determined (S103). The numbers of the wirings crossing the border of each divided region are equalized (S104). If the length of a side of each divided region is larger than a predetermined length (No in S105), that region is further divided (S102). If the length of a side of each region is smaller than the predetermined length, the route at that time is adopted as the rough wiring route of each wiring (S106).

Claims

1. A wiring design method for determining wiring routes between cells of an integrated circuit device, the wiring design method comprising:

region-divide step where a wiring-arrangement-target region is divided in both vertical and horizontal directions;

rough-arrange step where, divided regions for wiring arrangement is determined with respect to each of wirings out of the wiring-arrangement-target region divided in the region divide step; and

rearrange step where an alternative divided region for wiring arrangement is determined again in case wiring distribution among divided regions determined in the rough-arrange step is not uniform;

wherein wiring routes are determined within determined divided regions.

2. A wiring design method of an integrated circuit device according to claim 1, wherein, number of wirings that cross over boundaries of divided regions is counted with respect each boundary and in case inequality degree among count values is out of acceptable range, wiring arrangement is determined again in the rearrange step.

3. A wiring design method of an integrated circuit device according to claim 1, wherein the region-divide step, the rough-arrange step, and the rearrange step are repeated until size of divided regions are reduced to reach a predetermined value, and in region-divide step of second-time or thereafter, the divided regions are further divided in both vertical and horizontal directions.

4. A wiring design method of an integrated circuit device according to claim 2 further comprising:

noise-estimate step where a maximum value of crosstalk noises is estimated based on determined wiring arrangement; and

countermeasure step where crosstalk noises are reduced with respect to a wiring whose maximum value estimated at the noise-estimate step exceeds a predetermined value,

wherein the noise-estimate step and the countermeasure step are processed after the rearrange step.

5. A wiring design method for determining wiring routes between cells of an integrated circuit device, the wiring design method comprising:

region-divide step where a wiring-arrangement-target region is divided in both vertical and horizontal directions;

rough-arrange step where, divided regions for wiring arrangement is determined with respect to each of wirings out of the wiring-arrangement-target region divided in the region divide step;

noise-estimate step where a maximum value of crosstalk noises is estimated based on determined wiring arrangement; and

countermeasure step where crosstalk noises are reduced with respect to a wiring whose maximum value estimated at the noise predict step exceeds a predetermined value,

wherein wiring routes are determined within determined divided regions.

6. A wiring design method of integrated circuit device according to claim 5, wherein a maximum value of crosstalk noises is estimated with respect to a wiring such that occupancy rate of number of crossed-over divided regions shared with other wirings against total number of crossed-over divided regions is higher than a predetermined value in the noise-estimate step.

7. A wiring design method of integrated circuit device according to claim 5, wherein the noise-estimate step includes:

individual calculation step where a maximum value of crosstalk noises occurable to a target wiring is calculated for each crossed-over divided region shared with other wirings; and

sum-up step where maximum values calculated for all of crossed-over divided regions shared with other wirings with respect to the target wiring in the individual calculation step are summed up and a sum of the maximum values is regarded as a maximum value of crosstalk noises to occur to the target wiring.

8. A wiring design method of integrated circuit device according to claim 7, wherein there are performed following procedures for each of crossed-over divided regions shared with other wirings with respect to the target wiring in the individual calculation step:

a procedure that an aggressor wiring that generates and brings crosstalk noises to a target wiring is selected among wirings that share a divided region;

a procedure that a maximum value of crosstalk noises to be brought to the target wiring by a selected aggressor wiring is calculated; and

a procedure that a maximum value calculated is regarded as a maximum value of crosstalk noise to occur to the target wiring at a target divided region shared with other wirings.

9. A wiring design method of integrated circuit device according to claim 8, wherein among wirings that share a divided region with a target wiring, a wiring output-slew-rate of which is steepest is selected as aggressor wiring in the individual calculation step.

10. A wiring design method of integrated circuit device according to claim 8, wherein among wirings that share a divided region with a target wiring, a wiring that has a cell of highest output driving performance is selected as aggressor wiring in the individual calculation step.

11. A wiring design method of integrated circuit device according to claim 5, wherein a divided region on which a target wiring is arranged is changed to another in the countermeasure step.

12. A wiring design method of integrated circuit device according to claim 5, wherein, in the countermeasure step, limitation information is assigned to a target wiring, and when wiring routes are finally determined within a determined divided region, distance between the target wiring to which limitation information is assigned and other wirings that share the divided region with the target wiring is taken as wide as possible.

13. A wiring design system for determining wiring routes between cells of an integrated circuit device comprising:

region-divide unit for dividing a wiring-arrangement-target region in both vertical and horizontal directions;

rough-arrange unit for determining divided regions of the wiring-arrangement-target region on which each of wirings should be arranged; and

rearrange unit for determining an alternative divided region on which a wiring should be arranged in case wiring distribution among divided regions determined in the rough arrange step is not uniform;

wherein wiring routes are determined and arranged within determined divided regions.

14. A wiring design system for determining wiring routes between cells of an integrated circuit device comprising:

region-divide unit for dividing a wiring-arrangement-target region in both vertical and horizontal directions;

rough-arrange unit for determining a divided region of the wiring-arrangement-target region on which each of wirings should be arranged;

noise-estimate unit for estimating a maximum value of crosstalk noises based on determined wiring arrangement; and

countermeasure unit for reducing crosstalk noises with respect to a wiring whose maximum value estimated at the noise-estimate unit exceeds a predetermined value,

wherein wiring routes are determined and arranged within determined divided regions.

15. A computer program product used for executing wiring design of an integrated circuit device by a computer, the computer program product comprising:

a computer readable medium; and

a computer program stored on the computer readable medium, the computer program comprising;

region-divide step for dividing a wiring-arrangement-target region in both vertical and horizontal directions and assigning identification information to each of divided regions;

rough-arrange step for determining rough arrangement of each wiring defined in accordance with order that a wiring passes over divided regions divided in the region-divide step;

ununiformity-judge step for judging whether or not wiring distribution along with rough arrangement determined in the rough-arrange step has uniformity exceeding acceptable degree; and

rearrange step for determining again other way of rough arrangement of wirings in case wiring distribution is determined as exceeding the acceptable degree of ununiformity in the ununiformity-judge step.

16. A computer program product used for executing wiring design of an integrated circuit device by a computer according to claim 15, wherein the computer program further comprises size-judge step for judging whether or not size of a divided region is same as or smaller than a predetermined value and in case judged as not same as or smaller than the predetermined value, the computer program executes the region-divide step, rough-arrange step, ununiformity-judge step, and rearrange step, again.

17. A computer program product used for executing wiring design of an integrated circuit device by a computer, the computer program product comprising:

a computer readable medium; and

a computer program stored on the computer readable medium, the computer program comprising;

region-divide step for dividing a wiring-arrangement-target region in both vertical and horizontal directions and assigning identification information to each divided region;

rough-arrange step for determining rough arrangement of each wiring defined in accordance with order that a wiring passes over divided regions divided in the region-divide step;

noise-estimate step for estimating a maximum value of crosstalk noises based on determined wiring arrangement; and

countermeasure step for changing rough arrangement or assigning limitation information with respect to wiring whose maximum value estimated at the noise estimate step exceeds a predetermined value.