Method and apparatus for signaling between devices of a memory system

• US 20040054845A1
• Filed: 10/22/2001
• Published: 03/18/2004
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Granted Patent: US 7,484,064 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.

Claims

1. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus uses differential signaling and has a first data bus symbol time that is shorter than a first address and control bus symbol time of the first address and control bus.

2. The memory system of claim 1 further comprising:

a second memory component connected to the first address and control bus and to the first data bus.

3. The memory system of claim 1 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected to the first memory controller and to the second memory component, wherein the second data bus uses differential signaling and has a second data bus symbol time that is shorter than the first address and control bus symbol time of the first address and control bus.

4. The memory system of claim 1 wherein a quotient of the first data bus symbol time divided by the first address and control bus symbol time is less than or equal to ⅛

.

5. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component;

a first clock signal conductor connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus has a first data bus symbol time that is shorter than a first address and control bus symbol time of the first address and control bus and wherein the first address and control bus symbol time is shorter than a first clock signal cycle time of the first clock signal.

6. The memory system of claim 5 further comprising:

a second memory component connected to the first address and control bus, to the first clock signal conductor, and to the first data bus.

7. The memory system of claim 5 further comprising:

a second memory component connected to the first address and control bus and to the first clock signal conductor; and

a second data bus connected to the first memory controller and to the second memory component, wherein the second data bus uses differential signaling and has a second data bus symbol time that is shorter than the first address and control bus symbol time of the first address and control bus.

8. The memory system of claim 5 wherein a first quotient of the first data bus symbol time divided by the first address and control bus symbol time is less than or equal to ⅛

and a second quotient of the first address and control bus symbol time divided by the first clock signal cycle time is less than or equal to ½

.

9. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first memory component includes a first termination structure connected to the first data bus and wherein the first data bus has a first data bus symbol time that is shorter than a first address and control symbol time of the first address and control bus.

10. The memory system of claim 9 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected to the first memory controller and to the second memory component, wherein the second memory component includes a second termination structure connected to the second data bus and wherein the first data bus symbol time is shorter than the first address and control bus symbol time of the first address and control bus.

11. The memory system of claim 9 wherein the first memory controller includes a third termination structure connected to the first data bus.

12. The memory system of claim 9 wherein a quotient of the first data bus symbol time divided by the first address and control bus symbol time is less than or equal to 1/8.

13. The memory system of claim 9 wherein a calibration process is used to adjust a first termination value of the first termination structure.

14. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first memory component includes a first termination structure connected to the first data bus, wherein the first data bus uses differential signaling, and wherein the first address and control bus uses non-differential signaling.

15. The memory system of claim 14 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected to the first memory controller and to the second memory component, wherein the second memory component includes a second termination structure connected to the second data bus and wherein the second data bus uses differential signaling.

16. The memory system of claim 14 wherein the first memory controller includes a third termination structure connected to the first data bus.

17. The memory system of claim 14 wherein a calibration process is used to adjust a first termination value of the first termination structure.

18. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus uses differential signaling and wherein the first memory component accesses a first word stored in the first memory component, the first word being wider than a first data bus width of the first data bus.

19. The memory system of claim 18 further comprising:

a second memory component connected to the first address and control bus and to the first data bus.

20. The memory system of claim 18 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected to the first memory controller and to the second memory component, wherein the second data bus uses differential signaling and wherein the second memory component accesses a second word stored in the second memory component, the second word being wider than a second data bus width of the second data bus.

21. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first memory controller includes a first receive circuit having a first read timing adjustment subcircuit for adjusting a first adjustable read data sampling time point for first read data sampled from the first data bus and wherein the first data bus uses differential signaling.

22. The memory system of claim 21 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected the first memory controller and to the second memory component, wherein the first memory controller includes a second receive circuit having a second read timing adjustment subcircuit for adjusting a second adjustable read data sampling time point for second read data sampled from the second data bus and wherein the second data bus uses differential signaling.

23. The memory system of claim 21 wherein a calibration process is used to adjust the first adjustable read data sampling time point.

24. The memory system of claim 21 wherein the first memory controller contains a first transmit circuit having a first write timing adjustment subcircuit for adjusting a first adjustable write data driving time point for first write data driven on the first data bus.

25. A memory system comprising:

a first memory controller;

a first memory component;

a first address and control bus connected to the first memory controller and to the first memory component; and

a first data bus connected to the first memory controller and to the first memory component, wherein the first memory controller component includes a first receive circuit having a first read timing adjustment subcircuit for adjusting a first adjustable read data sampling time point for first read data sampled from the first data bus and wherein the first memory component includes a first termination structure connected to the first data bus.

26. The memory system of claim 25 further comprising:

a second memory component connected to the first address and control bus; and

a second data bus connected to the first memory controller and to the second memory component, wherein the first memory controller includes a second receive circuit having a second read timing adjustment subcircuit for adjusting a second adjustable read data sampling time point for second read data sampled from the second data bus and wherein the second memory component includes a second termination structure connected to the second data bus.

27. The memory system of claim 25 wherein a calibration process is used to adjust the first adjustable read data sampling time point.

28. The memory system of claim 25 wherein the first memory controller includes a first transmit circuit having a first write timing adjustment subcircuit for adjusting a first adjustable write data driving time point for first write data driven on the first data bus.

29. The memory system of claim 25 wherein the first memory controller includes a third termination structure connected to the first data bus.