Method and apparatus for signaling between devices of a memory system
First Claim
1. A memory system comprising:
- a first memory controller;
a first memory component;
a first address and control bus connected to the first memory controller and the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and
a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus uses differential signaling and has a first data bus symbol time that is shorter than a first address and control bus symbol time of the first address and control bus.
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Accused Products
Abstract
A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
254 Citations
36 Claims
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1. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus uses differential signaling and has a first data bus symbol time that is shorter than a first address and control bus symbol time of the first address and control bus. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; a first clock signal conductor connected to the first memory controller and to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus has a first data bus symbol time that is shorter than a first address and control bus symbol time of the first address and control bus and wherein the first address and control bus symbol time is shorter than a first clock signal cycle time of the first clock signal. - View Dependent Claims (7, 8, 9, 10)
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11. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first memory component includes a first termination structure connected to the first data bus and wherein the first data bus has a first data bus symbol time that is shorter than a first address and control symbol time of the first address and control bus. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first memory component includes a first termination structure connected to the first data bus, wherein the first data bus uses differential signaling, and wherein the first address and control bus uses non-differential signaling. - View Dependent Claims (18, 19, 20, 21)
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22. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first data bus uses differential signaling and wherein the first memory component accesses a first word stored in the first memory component, the first word being wider than a first data bus width of the first data bus. - View Dependent Claims (23, 24, 25)
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26. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first memory controller includes a first receive circuit having a first read timing adjustment subcircuit for adjusting a first adjustable read data sampling time point for first read data sampled from the first data bus and wherein the first data bus uses differential signaling. - View Dependent Claims (27, 28, 29, 30)
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31. A memory system comprising:
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a first memory controller; a first memory component; a first address and control bus connected to the first memory controller and to the first memory component, the first address and control bus including a plurality of signal conductors that extend from the first memory controller to the first memory component; and a first data bus connected to the first memory controller and to the first memory component, wherein the first memory controller component includes a first receive circuit having a first read timing adjustment subcircuit for adjusting a first adjustable read data sampling time point for first read data sampled from the first data bus and wherein the first memory component includes a first termination structure connected to the first data bus. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification