Mechanism for remapping post virtual machine memory pages

• US 20040128469A1
• Filed: 12/27/2002
• Published: 07/01/2004
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Campbell, Randolph L., Hall, Clifford D.
• Granted Patent: US 7,900,017 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Claims

1. A computer system comprising:

a processor;

a chipset, coupled to the processor, to translate partitioned virtual machine memory addresses received from the processor to page level addresses; and

a memory device coupled to the chipset.

2. The computer of claim 1 wherein the chipset comprises a translation lookaside buffer (TLB) that translates the partitioned machine memory addresses to the page level addresses.

3. The computer of claim 2 wherein the TLB comprises:

an input that receives a partitioned address;

a remap directory coupled to the input;

a remap table coupled to the directory and the input; and

an output, coupled to the remap table, that transmits a physical address.

4. The computer of claim 3 wherein the memory device comprises:

remap tables to translate the partitioned virtual machine addresses into physical memory addresses; and

page tables to specify the remapping of partitioned virtual machine addresses to page level addresses.

5. The computer of claim 2 wherein the TLB further comprises:

a bus master device; and

an offset register coupled to the bus master device and the TLB.

6. The computer of claim 5 wherein the TLB controls the bus master device permission to access the memory based upon a flag bit within the TLB base address.

7. The computer of claim 6 wherein the bus master device is a graphics controller.

8. The computer of claim 6 wherein the bus master device is a disk controller.

9. A chipset comprising a translation lookaside buffer (TLB) to translate partitioned machine memory addresses received from a processor into page level addresses.

10. The chipset of claim 9 wherein the TLB comprises:

an input that receives a partitioned address;

a remap directory coupled to the input;

a remap table coupled to the directory and the input; and

an output, coupled to the remap table, to transmit a physical address to a memory device.

11. The chipset of claim 10 wherein the TLB further comprises:

a bus master device; and

an offset register coupled to the bus master device and the first TLB.

12. The chipset of claim 11 wherein the TLB controls the bus master device permission to access the memory based upon a flag bit within the TLB base address.

13. The chipset of claim 11 wherein the bus master device is a graphics controller.

14. The computer of claim 11 wherein the bus master device is a disk controller.

15. A method comprising:

receiving a partitioned virtual machine memory address at a chipset; and

translating the partitioned virtual machine memory addresses received from the processor to page level addresses at the chipset.

16. The method of claim 15 further comprising:

translating a logical address to a virtual machine memory physical address at a processor; and

translating the virtual machine memory physical address to a partitioned virtual machine memory address.

17. The method of claim 16 further comprising transmitting the partitioned virtual machine memory address to the chipset.