Mechanism for remapping post virtual machine memory pages

• US 7,900,017 B2
• Filed: 12/27/2002
• Issued: 03/01/2011
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Campbell, Randolph L., Hall, Clifford D.
• Primary Examiner(s): Thomas; Shane M
• Application Number:
  US10/330,986
• Publication Number:
  US 20040128469A1
• Time in Patent Office: 2,986 Days
• Field of Search: 711/207, 711/209, 711/205, 711/6, 711/E12.061, 711/E12.068
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Claims

1. A computer system comprising:

a memory to store a plurality of page tables and a plurality of remap tables;

a processor, including partitioning logic and a first translation lookaside buffer, the partitioning logic to partition the memory by dividing the memory into a plurality of contiguous regions and allocating each one of the plurality of contiguous regions to each one of a plurality of virtual machines, the first translation lookaside buffer to cache page table entries from the plurality of page tables;

an input/output device; and

a chipset, coupled to the processor and the input/output device, including a second translation lookaside buffer to cache remap table entries from the plurality of remap tables, the second translation lookaside buffer and the plurality of remap tables to circumvent the partitioning by remapping memory addresses from the processor and the input/output device at page level granularity, where page size is less than region size.

2. The computer system of claim 1 wherein the second translation lookaside buffer and the plurality of remap tables are to circumvent the partitioning by translating partitioned memory addresses to physical memory addresses.

3. The computer system of claim 2 wherein the second translation lookaside buffer comprises:

an input that receives a partitioned memory address;

a remap directory coupled to the input;

a remap table coupled to the directory and the input; and

an output, coupled to the remap table, that transmits a physical memory address.

4. The computer system of claim 2 further comprising:

an offset register coupled to the input/output device and the second translation lookaside buffer.

5. The computer system of claim 4 wherein the second translation lookaside buffer controls the input/output device'"'"'s permission to access the memory.

6. The computer system of claim 5 wherein the input/output device is a graphics controller.

7. The computer system of claim 5 wherein the input/output device is a disk controller.

8. A method comprising:

using a processor, having a first translation lookaside buffer, to partition a memory by dividing the memory into a plurality of contiguous regions and allocating each one of the plurality of contiguous regions to each one of a plurality of virtual machines sharing the processor;

using a second translation lookaside buffer in a chipset and a plurality of remap tables in the memory to circumvent the partitioning by remapping memory addresses from the processor at page level granularity, where the page size is less than the region size; and

remapping memory addresses from an input/output device using the second translation lookaside buffer.

9. The method of claim 8

wherein partitioning includes translating a logical address to a partitioned memory address at the processor;

and

circumventing the partitioning includes translating the partitioned memory address to a physical memory address at the chipset.