Data processing structure

• US 20040139263A1
• Filed: 11/20/2003
• Published: 07/15/2004
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Wittenstein AG
• Original Assignee: Wittenstein AG
• Inventors: Krug, Andreas, Kalker, Thomas
• Granted Patent: US 7,047,342 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: B25J 9/1602 characterised by the control system, structure, architecture
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G05B 19/4148 characterised by using several processors for different functions, distributed (real-time) systems G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33168 Two bus, master bus and local servo bus
• CPC Class Codes: G05B 2219/33281 Archictecture, nodes for communication and measuring on serial bus

Abstract

The invention relates to a data processing structure comprising a plurality of processors (20i) and a data bus (100) for a data communication with a serial data structure. The plurality of processors (20i) can be respectively coupled in parallel to the data bus (100), and a data communication via said data bus (100) with one of the processors (20i), preferably a programniing of said processor (20i), is authorised for the same (20i), but is blocked for all of the other (20j) processors.

Claims

1. A data processing structure having a plurality of processors (20i) and a data bus (100) for data communication with a serial data structure, characterized in that the plurality of processors (20i) can each be connected to the data bus (100) in a parallel connection, and data communication via the data bus (100) with one of the plurality of processors (20i), preferably comprising programming this processor (20i), is permitted for this processor (20i) and prohibited for all the others (20j) of the plurality of processors.

2. The data processing structure as claimed in claim 1, characterized in that, for the data communication via the data bus (100) with one of the plurality of processors (20i), this processor (20i) is connected to the data bus (100) while all the others (20j) of the plurality of processors are disconnected from the data bus (100).

3. The data processing structure as claimed in claim 1 or 2, characterized in that in each case one switching unit (120i) is connected between each processor (20i) and the data bus (100), the switching unit (120i) either connecting the processor (20i) to the data bus (100) or disconnecting it from the data bus (100).

4. The data processing structure as claimed in claim 3, characterized in that the plurality of processors (20i) can be controlled by means of a field bus (30) in a parallel connection.

5. The data processing structure as claimed in claim 4, characterized in that

each processor (20i) is assigned in each case one control unit (110i),

the control units (110i) are connected to the field bus (30), and

the control units (110i) can receive control signals via the field bus (30) in order either to connect the respective processors (20i) to the data bus (100) via the associated switching units (120i), or disconnect them from the data bus (100).

7. A drive controller, preferably for a robot, having a data processing structure according to one of the preceding claims.

6. A data processing structure having a plurality of processors (20i) which can be controlled via a field bus (30) in a parallel connection, and a data bus (100) for data communication with a serial data structure, characterized in that the plurality of processors (20i) can be connected both to the field bus (30) and to the data bus (100), in each case in a parallel connection, and

for data communication with one of the plurality of processors (20i) via the data bus (100), this processor (20i) is connected to the data bus (100), while all the others (20j) of the plurality of processors are disconnected from the data bus (100).

8. A method for data communication in a data processing structure having a plurality of processors (20i) and a data bus (100) for data communication with a serial data structure, the plurality of processors (20i) being capable of being connected to the data bus (100) in each case in a parallel connection, characterized by the steps:

(a) data communication via the data bus (100) is permitted for one (20i) of the plurality of processors, and

(b) data communication via the data bus (100) is simultaneously prohibited for all the others (20j) of the plurality of processors.

9. The method as claimed in claim 8, characterized in that the data communication via the data bus (100) for the one (20i) of the plurality of processors comprises programming this processor (20i).