Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit

• US 6,825,699 B2
• Filed: 01/31/2003
• Issued: 11/30/2004
• Est. Priority Date: 01/31/2003
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Erickson, Ian, Cogdill, Michael H., Marshall, David John
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/355,437
• Publication Number:
  US 20040150009A1
• Time in Patent Office: 669 Days
• Field of Search: 327/108, 327/112, 327/390, 327/536, 327/538, 327/544, 327/427, 327/434, 326/82, 326/83, 326/88, 326/113
• US Class Current: 327/108
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.

Claims

1. A buffer comprising:

a) an input node;

b) an output node;

a first transistor comprising a first transistor first node connected to said input node, a first transistor second node connected to said output node, and a first transistor control node;

a second transistor comprising a second transistor first node connected to a first predetermined voltage node, a second transistor second node connected to said first transistor control node, and a second transistor control node connected to said first predetermined voltage node;

a capacitive element connected between said second transistor first node and said output node; and

a third transistor comprising a third transistor first node connected to said second transistor, second node, a third transistor second node connected to a second predetermined voltage node, and a third transistor control node connected to a third preselected voltage node.

2. The buffer of claim 1, wherein the capacitive element comprises a transistor comprising a drain node coupled to a source node and the said output node, and a gate node coupled to said first transistor control node.

3. The buffer of claim 1, wherein said first transistor, the said second transistor, and said third transistor are n-type field effect transistors.

4. The buffer of claim 1, wherein said first transistor, the said second transistor, and the said third transistor are p-type field effect transistors.

5. The buffer of claim 1 wherein the buffer is a full logic level passive buffer.

6. The buffer of claim 1, wherein said first predetermined voltage node is connectable to a v_DD voltage.

7. The buffer of claim 1, wherein:

said first transistor first node is a drain, said first transistor second node is a source, and said first transistor control node is a gate;

said second transistor first node is a drain, said second transistor second node is a source, and said second transistor control node is a gate; and

said third transistor first node is a drain, said third transistor second node is a source, and said third transistor control node is a gate.

8. The buffer of claim 1, wherein;

said first transistor first node is a source, said first transistor second node is a drain, and said first transistor control node is a gate;

said second transistor first node is a source, said second transistor second node is a drain, and said second transistor control node is a gate; and

said third transistor first node is a source, said third transistor second node is a drain, and said third transistor control node is a gate.

9. The buffer of claim 1, wherein said second predetermined voltage node is connectable to a ground node.