Flat panel display device with polycrystalline silicon thin film transistor

• US 20040245526A1
• Filed: 02/18/2004
• Published: 12/09/2004
• Est. Priority Date: 06/05/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Lee, Ki-Yong, Park, Ji-Yong, Koo, Jae-Bon, Lee, Ul-Ho, Park, Hye-Hyang
• Granted Patent: US 7,297,980 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit portion and active channel regions of pixel portion. This may be achieved by having a different number of grain boundaries included in the polycrystalline silicon thin film formed in active channel regions of a switching thin film transistor and a driving thin film transistor formed in the pixel portion, and by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a thin film transistor for driving the pixel portion for each red, green and blue of the pixel portion. Further, this may be achieved by having a different number of grain boundaries included in polycrystalline silicon formed in active channel regions of an NMOS thin film transistor and a PMOS thin film transistor for forming CMOS transistor used in flat panel display device, thereby constructing a thin film transistor to obtain the improved characteristics for each transistor.

Claims

1. A flat panel display device with polycrystalline silicon thin film transistor comprising:

a pixel portion divided into gate lines and data lines and equipped with a thin film transistor driven by signals applyed by the gate lines and data lines; and

a driving circuit portion comprising one or more thin film transistors connected to the gate lines and data lines respectively to apply signals to the pixel portion, wherein the average number of grain boundaries of polycrystalline silicon which are formed in active channel regions of the one or more thin film transistors installed at the driving circuit portion and meet a current direction line is at least one or more less than the average number of grain boundaries of polycrystalline silicon which are formed in active channel regions of the thin film transistor installed at the pixel portion and meet a current direction line for a unit area of active channels.

2. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein a shape of the grains of polycrystalline silicon is anisotropic, and the grain boundaries are primary grain boundaries.

3. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein a shape of the grains of polycrystalline silicon is anisotropic, and the grain boundaries are side grain boundaries of anisotropic grains.

4. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the one or more thin film transistors installed at the driving circuit portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

;

the polycrystalline silicon grain boundaries formed in active channel regions of the thin film transistor installed at the pixel portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

; and

the length of the active channels of the thin film transistor installed at the pixel portion is II longer than length of the active channels of the one or more thin film transistor installed at the driving circuit portion.

5. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the one or more thin film transistors installed at the driving circuit portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of 45 to 135°

; and

the polycrystalline silicon grain boundaries formed in active channel regions of the thin film transistor installed at the pixel portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

.

6. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the one or more thin film transistors installed at the driving circuit portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

;

the polycrystalline silicon grain boundaries formed in active channel regions of the thin film transistor installed at the pixel portion are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

; and

the length of the active channels of the thin film transistor installed at the pixel portion is the same as length of the active channels of the thin film transistor installed at the driving circuit portion.

7. The flat panel display device with polycrystalline silicon thin film transistor according to claim 2, wherein the polycrystalline silicon is fabricated by a sequential lateral solidification method.

8. The flat panel display device with polycrystalline silicon thin film transistor according to claim 3, wherein the polycrystalline silicon is fabricated by a metal induced lateral crystallization method.

9. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein shape of the grains of polycrystalline silicon is isotropic.

10. The flat panel display device with polycrystalline silicon thin film transistor according to claim 7, wherein a length of the active channels of the thin film transistor installed at the pixel portion is the same as length of the active channels of the one or more thin film transistors installed at the driving circuit portion.

11. The flat panel display device with polycrystalline silicon thin film transistor according to claim 7, wherein the polycrystalline silicon is formed by eximer laser annealing.

12. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein the average grain size of polycrystalline silicon grains included in active channel region of a gate in the driving circuit portion is larger than that of polycrystalline silicon grains included in active channel region of a gate in the pixel portion.

13. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein the flat panel display device is one of an organic electroluminscent device and a liquid crystal display device.

14. A flat panel display device with polycrystalline silicon thin film transistor comprising:

a switching thin film transistor for transmitting data signals; and

a driving thin film transistor for driving the organic electroluminescent device so that a certain amount of current flows through organic electroluminescent device according to the data signals, wherein the average number of grain boundaries of polycrystalline silicon which are formed in active channel regions of the driving thin film transistor and meet a current direction line is at least one or more greater than the average number of grain boundaries of polycrystalline silicon which are formed in active channel regions of the switching thin film transistor and meet a current direction line for a unit area of active channels.

15. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein a shape of the grains of polycrystalline silicon is anisotropic, and the grain boundaries are primary grain boundaries.

16. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein a shape of the grains of polycrystalline silicon is anisotropic, and the grain boundaries are side grain boundaries of anisotropic grains.

17. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the switching thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

;

the polycrystalline silicon grain boundaries formed in active channel regions of the driving thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

; and

the length of the active channels of the driving thin film transistor is longer than length of the active channels of the switching thin film transistor.

18. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the switching thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of 45 to 135°

; and

the polycrystalline silicon grain boundaries formed in active channel regions of the driving thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

.

19. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein:

the polycrystalline silicon grain boundaries formed in active channel regions of the switching thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

;

the polycrystalline silicon grain boundaries formed in active channel regions of the driving thin film transistor are arranged in such a way that the polycrystalline silicon grain boundaries are inclined to the current direction line at an angle of −

45 to 45°

; and

the length of the active channels of the driving thin film transistor is the same as length of the active channels of the switching thin film transistor.

20. The flat panel display device with polycrystalline silicon thin film transistor according to claim 15, wherein the polycrystalline silicon is fabricated by a sequential lateral solidification method.

21. The flat panel display device with polycrystalline silicon thin film transistor according to claim 16, wherein the polycrystalline silicon is fabricated by a metal induced lateral crystallization method.

22. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein shape of the grains of polycrystalline silicon is isotropic.

23. The flat panel display device with polycrystalline silicon thin film transistor according to claim 22, wherein a length of the active channels of the driving thin film transistor is the same as length of the active channels of the switching thin film transistor.

24. The flat panel display device with polycrystalline silicon thin film transistor according to claim 22, wherein the polycrystalline silicon is formed by eximer laser annealing.

25. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein the average grain size of polycrystalline silicon grains included in active channel region of a gate in the switching thin film transistor is larger than that of polycrystalline silicon grains included in active channel region of a gate in the driving thin film transistor.

26. The flat panel display device with polycrystalline silicon thin film transistor according to claim 14, wherein the flat panel display device is one of an organic electroluminscent device and a liquid crystal display device.

27. A CMOS thin film transistor characterized in that a P type thin film transistor and an N type thin film transistor have a different number of primary grain boundaries of polycrystalline silicon included in active channel regions, and the number of grain boundaries included in the P type thin film transistor is at least one or more less than the number of grain is boundaries included in the N type thin film transistor.

28. The CMOS thin film transistor according to claim 27, wherein channel length of the P type thin film transistor is the same as that of the N type thin film transistor.

29. The CMOS thin film transistor according to claim 27, wherein the primary grain boundaries of polycrystalline silicon included in the active channel regions of the N type thin film transistor and P type thin film transistor are perpendicular to a current flow direction.

30. The CMOS thin film transistor according to claim 27, wherein the polycrystalline silicon is fabricated by a sequential lateral solidification crystallization method.

31. The CMOS thin film transistor according to claim 27, wherein the primary grain boundaries are not included in the P type thin film transistor.

32. The CMOS thin film transistor according to claim 27, wherein the number of primary grain boundaries included in the P type thin film transistor is 2 or less.

33. The CMOS thin film transistor according to claim 32, wherein the number of primary grain boundaries included in the N type thin film transistor is 6, and the number of primary grain boundaries included in the P type thin film transistor is 2.

34. The CMOS thin film transistor according to claim 27, wherein the CMOS thin film transistor includes one of an LDD structure an off-set structure.

35. A display device using the CMOS thin film transistor of claim 27.

36. The display device according to claim 35, wherein the display device is one of a liquid crystal display device and an organic electroluminescent display device.

37. A flat panel display device comprising green, red and blue pixel regions, and driving thin film transistor for driving each of the pixels having the same length and width of active channels, wherein the number of grain boundaries of polycrystalline silicon included in active channel regions of the driving thin film transistor is different from each other for each pixel.

38. The flat panel display device according to claim 37, wherein the green pixel region has the largest number of the primary grain boundaries of polycrystalline silicon, and the red pixel region and the blue pixel region have the same number of the primary grain boundaries of polycrystalline silicon.

39. The flat panel display device according to claim 37, wherein the number of the primary grain boundaries of polycrystalline silicon is increased in the order of green, blue and red pixel regions.

40. The flat panel display device according to claim 37, wherein the green pixel region and the blue pixel region have the same number of the primary grain boundaries of polycrystalline silicon, and the red pixel region has the smallest number of the primary grain boundaries of polycrystalline silicon.

41. The flat panel display device according to claim 37, wherein the grain boundaries are perpendicular to current flowing direction in active channel regions of each driving thin film transistor.

42. The flat panel display device according to claim 41, wherein the grain boundaries are primary grain boundaries.

43. The flat panel display device according to claim 41, wherein the grain boundaries are side grain boundaries of anisotropic grains.

44. The flat panel display device according to claim 43, wherein the flat panel display device has the smallest number of primary grain boundaries included in active channel regions of driving thin film transistor of the green pixel region.

45. The flat panel display device according to claim 44, wherein the number of primary grain boundaries included in active channel regions of driving thin film transistor of the blue pixel region is the same as or less than the number of primary grain boundaries included in active channel regions of driving thin film transistor of the red pixel region.

46. The flat panel display device according to claim 37, wherein the flat panel display device is one of a liquid crystal display device, an inorganic electroluminescent device and an organic electroluminescent device.