Flat panel display device with polycrystalline silicon thin film transistor

• US 7,297,980 B2
• Filed: 02/18/2004
• Issued: 11/20/2007
• Est. Priority Date: 06/05/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Lee, Ki-Yong, Park, Ji-Yong, Koo, Jae-Bon, Lee, Ul-Ho, Park, Hye-Hyang
• Primary Examiner(s): Landau; Matthew C.
• Application Number:
  US10/779,781
• Publication Number:
  US 20040245526A1
• Time in Patent Office: 1,371 Days
• Field of Search: 257/63, 257/66, 257/72, 257/75, 257/64, 257/70, 257/E29.273, 257E29292-E29294, 349/43
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit portion and active channel regions of pixel portion. This may be achieved by having a different number of grain boundaries included in the polycrystalline silicon thin film formed in active channel regions of a switching thin film transistor and a driving thin film transistor formed in the pixel portion, and by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a thin film transistor for driving the pixel portion for each red, green and blue of the pixel portion. Further, this may be achieved by having a different number of grain boundaries included in polycrystalline silicon formed in active channel regions of an NMOS thin film transistor and a PMOS thin film transistor for forming CMOS transistor used in flat panel display device, thereby constructing a thin film transistor to obtain the improved characteristics for each transistor.

Claims

1. A flat panel display device with polycrystalline silicon thin film transistors, comprising:

a pixel portion divided by gate lines and data lines and comprising thin film transistors driven by signals applied by the gate lines and data lines; and

a driving circuit portion comprising thin film transistors connected to the gate lines and data lines respectively to apply signals to the pixel portion,

wherein an average number of grain boundaries of polycrystalline silicon formed in an active channel region of each thin film transistor installed at the driving circuit portion and meet a current direction line is at least one or more less than an average number of grain boundaries of polycrystalline silicon formed in an active channel region of each thin film transistor installed at the pixel portion and meet a current direction line for a unit area of active channels,

wherein the polycrystalline silicon grain boundaries formed in the active channel region of each thin film transistor installed at the driving circuit portion include primary polycrystalline silicon grain boundaries that are inclined to the current direction line at an angle of about −

45 to 45°

,

wherein the polycrystalline silicon grain boundaries formed in the active channel region of each thin film transistor installed at the pixel portion include primary polycrystalline silicon grain boundaries that are inclined to the current direction line at an angle of about −

45 to 45°

, and

wherein the active channel of each thin film transistor installed at the pixel portion is longer than the active channel of each thin film transistor installed at the driving circuit portion.

2. The flat panel display device with polycrystalline silicon thin film transistor according to claim 1, wherein a shape of the grains of polycrystalline silicon is anisotropic, and the grain boundaries are primary grain boundaries.

3. The flat panel display device with polycrystalline silicon thin film transistor according to claim 2, wherein the polycrystalline silicon is fabricated by a sequential lateral solidification method.

4. The flat panel display device with polycrystalline silicon thin film transistors according to claim 1, wherein a shape of the grains of polycrystalline silicon is an isotropic, and the grain boundaries include side grain boundaries of anisotropic grains.

5. The flat panel display device with polycrystalline silicon thin film transistors according to claim 4, wherein the polycrystalline silicon is fabricated by a metal induced lateral crystallization method.

6. The flat panel display device with polycrystalline silicon thin film transistors according to claim 1, wherein the flat panel display device is one of an organic electroluminescent device and a liquid crystal display device.