Video signal frame rate modifier and method for 3D video applications

• US 20040252756A1
• Filed: 06/10/2003
• Published: 12/16/2004
• Est. Priority Date: 06/10/2003
• Status: Abandoned Application

• Current Assignee: i-O Display Systems LLC (Ilixco, Inc.)
• Original Assignee: i-O Display Systems LLC (Ilixco, Inc.)
• Inventors: Holloway, Marty M., Smith, David
• Application Number:
  US10/457,999
• Publication Number:
  US 20040252756A1
• Time in Patent Office: Days
• US Class Current: 375/240.01
• CPC Class Codes: H04N 13/139 Format conversion, e.g. of frame-rate or size

Abstract

A assembly that modifies the frame rate of a 3D video signal and corresponding method are disclosed. The frame rate of the video signal can be increased by clocking a video encoder at a desired clock rate. When viewing a display of the video signal with the increased frame rate through a pair of stereo glasses, the perception of flicker can be reduced or eliminated.

Claims

1. A video signal frame rate modifying assembly for modifying a frame rate of a native video signal for use in a stereo display system, the native video signal containing alternating left and right eye images, comprising:

a clock signal generator for generating a clock signal, the clock signal having a frequency of a desired frame rate for an output video signal of the video signal frame rate modifying assembly; and

a video encoder for receiving the native video signal and increasing a frame rate of the native video signal to the desired frame rate based on the clock signal, the increased frame rate video signal output as the output video signal.

2. The video signal frame rate modifying assembly according to claim 1, wherein the video encoder converts the native video signal from a digital signal to an analog signal.

3. The video signal frame rate modifying assembly according to claim 2, wherein the conversion from digital to analog is carried out at the frequency of the clock signal.

4. The video signal frame rate modifying assembly according to claim 3, wherein:

for each left eye image of the native video signal, the video encoder buffers two output left eye frames;

for each right eye image of the native video signal, the video encoder buffers two output right eye frames; and

the buffered left and right eye frames are output in alternating fashion as the output video signal.

5. The video signal frame rate modifying assembly according to claim 1, wherein:

for each left eye image of the native video signal, the video encoder buffers two output left eye frames;

for each right eye image of the native video signal, the video encoder buffers two output right eye frames; and

the buffered left and right eye frames are output in alternating fashion as the output video signal.

6. The video signal frame rate modifying assembly according to claim 1, wherein the clock signal generated by the clock signal generator is phase-locked to a clock signal associated with the native video signal.

7. The video signal frame rate modifying assembly according to claim 1, wherein the clock signal generator is a clock multiplier configured to increase a clock signal associated with the native video signal by a factor of two.

8. A two-dimensional (2D) to three-dimensional (3)D video signal transformer assembly, comprising:

a video decoder for receiving an analog input video signal having a native frame rate and converting the input video signal to a digital video signal at the native frame rate;

a video processor for executing logic to convert the decoded video signal from a 2D format to a 3D format and outputting a processed video signal at the native frame rate and having alternating left and right eye images; and

a video encoder that is clocked at a multiple of the native frame rate, the video encoder for converting the processed video signal from a digital format to an analog output video signal at the multiplied frame rate.

9. The 2D to 3D video signal transformer assembly according to claim 8, wherein:

for each left eye image of the processed video signal, the video encoder buffers two output left eye frames;

for each right eye image of the processed video signal, the video encoder buffers two output right eye frames; and

the buffered left and right eye frames are output in alternating fashion as the output video signal.

10. The 2D to 3D video signal transformer assembly according to claim 8, further comprising a clock multiplier for increasing a clock signal associated with the native video signal to generate a clock signal used to clock the video encoder.

11. The 2D to 3D video signal transformer assembly according to claim 10, wherein the clock signal associated with the native video signal is increased by a factor of two.

12. A method of modifying a frame rate of a native video signal for use in a stereo display system, the native video signal containing alternating left and right eye images, comprising:

generating a clock signal having a frequency of a desired frame rate for an output video signal, the output video signal adapted for display by a display assembly; and

increasing the frame rate of the native video signal based on the clock signal and outputting the increased frame rate video signal as the output video signal.

13. The method according to claim 12, further comprising converting the native video signal from a digital signal to an analog signal.

14. The method according to claim 13, wherein the conversion from digital to analog is carried out at a frequency of the clock signal.

15. The method according to claim 14, further comprising:

buffering two output left eye frames for each left eye image of the native video signal;

buffering two output right eye frames for each right eye image of the native video signal; and

outputting the buffered left and right eye frames in alternating fashion as the output video signal.

16. The method according to claim 12, further comprising:

buffering two output left eye frames for each left eye image of the native video signal;

buffering two output right eye frames for each right eye image of the native video signal; and

outputting the buffered left and right eye frames in alternating fashion as the output video signal.

17. The method according to claim 12, wherein the generated clock signal is phase-locked to a clock signal associated with the native video signal.

18. The method according to claim 12, wherein the frame rate of the output video signal is twice the frame rate of the native video signal.

19. A method of converting a two-dimensional (2D) video signal to a three-dimensional (3)D video signal, comprising:

decoding a received analog input video signal having a native frame rate, the decoding including converting the input video signal to a digital video signal at the native frame rate;

converting the decoded video signal from a 2D format to a 3D format to generate a processed video signal at the native frame rate and having alternating left and right eye images; and

encoding the processed video signal at a multiple of the native frame rate, the encoding converting the processed video signal from a digital format to an analog output video signal at the multiplied frame rate.

20. The method according to claim 19, further comprising:

buffering two output left eye frames for each left eye image of the processed video signal;

buffering two output right eye frames for each right eye image of the processed video signal; and

outputting the buffered left and right eye frames in alternating fashion as the output video signal.

21. The method according to claim 19, further comprising generating a clock signal for driving the encoding by increasing a frequency of a clock signal associated with the native video signal.

22. The method according to claim 19, wherein the output video signal has a frame rate that is twice the frame rate of the input video signal.

23. A video signal frame rate modifying assembly for modifying a frame rate of a native video signal for use in a stereo display system, the native video signal containing alternating left and right eye images, comprising a video encoder for receiving the native video signal and increasing a frame rate of the native video signal to provide an output video signal, and an input to the video encoder to indicate the increased frame rate.