Semiconductor integrated circuit
First Claim
1. A semiconductor integrated circuit, comprising:
- a first circuit that delays a clock signal in stages;
a second circuit that selects one from a plurality of delay clock signals being provided with different delays in the first circuit; and
a third circuit that generates a double multiplied clock signal of which a frequency is doubled from of a frequency of the clock signal, based on a clock signal inputted to the first circuit and the delay clock signal selected by the second circuit.
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Accused Products
Abstract
The invention provides a semiconductor integrated circuit incorporating a clock signal multiplying circuit which can generate a double multiplied clock signal in following up changes in power voltage and a frequency of a reference clock signal without using a phase comparator. The semiconductor integrated circuit can include first circuits which delay clock signals in stages, a second circuit which selects one of a plurality of delay clock signals which have been provided with different delays in the first circuits, and a third circuit which generates a double multiplied clock signal with a frequency double the clock signal based on a delay clock signal selected by the clock signals inputted to the first circuits and the second circuit.
18 Citations
6 Claims
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1. A semiconductor integrated circuit, comprising:
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a first circuit that delays a clock signal in stages;
a second circuit that selects one from a plurality of delay clock signals being provided with different delays in the first circuit; and
a third circuit that generates a double multiplied clock signal of which a frequency is doubled from of a frequency of the clock signal, based on a clock signal inputted to the first circuit and the delay clock signal selected by the second circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification