Novel embedded dual-port DRAM process
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Abstract
A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
23 Citations
27 Claims
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1-18. -18. (Canceled).
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19. An integrated circuit device comprising:
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a plurality of MOS devices wherein a plurality of STI regions in a substrate separate said MOS devices; and
an array of DRAM cells each comprising;
a capacitor comprising a trench in said substrate wherein said trench is lined by a dielectric layer, wherein said trench is filled by a conductive layer overlying said dielectric layer, and wherein said trench is etched at the same time as trenches for said STI regions; and
access transistors having gate, drain, and source terminals wherein said gate terminals comprise said conductive layer. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification