Embedded dual-port DRAM process

• US 7,091,543 B2
• Filed: 08/18/2004
• Issued: 08/15/2006
• Est. Priority Date: 05/15/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, Ming-Hsiang, Chiang, Wen-Chuan, Sinitsky, Dennis J., Tzeng, Kuo-Chyuan
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US10/920,492
• Publication Number:
  US 20050017285A1
• Time in Patent Office: 727 Days
• Field of Search: 257/68, 257/71, 257/296, 257/301, 257E27084-E27097, 257/E27.075, 438/243, 438/386
• US Class Current: 257/301
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

Claims

1. An integrated circuit device comprising:

a plurality of MOS devices wherein a plurality of STI regions in a substrate separate said MOS devices; and

an array of DRAM cells each comprising;

a capacitor comprising a trench in said substrate wherein said trench is lined by a dielectric layer, wherein said trench is filled by a conductive layer overlying said dielectric layer, and wherein said trench is etched at the same time as trenches for said STI regions; and

access transistors having gate, drain, and source terminals wherein said gate terminals comprise said conductive layer;

wherein said substrate comprises a core area, an I/O area, and a DRAM area, each of said core area, said I/O area, and said DRAM area has a gate oxide layer, and said gate oxide layer comprises a different thickness for each of said areas.

2. The device according to claim 1 further comprising inert ions in said trench.

3. The device according to claim 1 wherein said inert ions comprise nitrogen.

4. The device according to claim 1 further comprising dopant ions in said trench.

5. The device according to claim 1 further comprising well regions underlying said DRAM cells.

6. The device according to claim 1 further comprising:

lightly doped source and drain regions for said transistors; and

spacers on sidewalls of said transistor gate terminals.

7. The device according to claim 1 wherein said dielectric layer comprises silicon oxide.

8. The device according to claim 1 wherein said conductive layer comprises polysilicon.

9. The device according to claim 1, wherein said drain terminals of said access transistors in each DRAM cell are coupled to bit lines, and said source terminals are coupled to a plate inversion layer under said dielectric layer.