Semiconductor device and method of manufacturing the same

• US 20050093089A1
• Filed: 11/24/2004
• Published: 05/05/2005
• Est. Priority Date: 07/27/1995
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Takayuki, Arai, Masatoshi, Yamashita, Kyoji, Nakabayashi, Takashi, Matsumoto, Michikazu, Miyanaga, Isao, Segawa, Mizuki, Yabu, Toshiki, Uehara, Takashi, Ukeda, Takaaki
• Granted Patent: US 7,126,174 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Claims

1-38. -38. (canceled)

39. A semiconductor device, comprising:

an isolation insulating area surrounding an active area of a semiconductor substrate;

a gate insulating film formed over the active area;

a gate electrode formed over the gate insulating film;

first L-shaped sidewalls formed over the side surfaces of the gate electrode; and

first silicide layers formed on regions located on the sides of the first L-shaped sidewalls within the active area.

40. The semiconductor device of claim 39, wherein the first L-shaped sidewalls are made of a silicon nitride film.

41. The semiconductor device of claim 39, further comprising first protection oxide films formed between the gate electrode and the first L-shaped sidewalls.

42. The semiconductor device of claim 39, further comprising a second silicide layer formed on the gate electrode.

43. The semiconductor device of claim 39, further comprising source/drain regions formed on both sides of the gate electrode within the active area,

wherein the first silicide layers are formed on the source/drain regions.

44. The semiconductor device of claim 39, further comprising an interconnection formed over the isolation insulating area;

and

second L-shaped sidewalls formed over the side surfaces of the interconnection.

45. The semiconductor device of claim 44, the second L-shaped sidewalls are made of a silicon nitride film.

46. The semiconductor device of claim 44, further comprising second protection oxide films formed between the interconnection and the second L-shaped sidewalls.

47. The semiconductor device of claim 44, further comprising a third silicide layer formed on the interconnection.

48. The semiconductor device of claim 39, wherein the isolation insulating area is a trench isolation.

49. The semiconductor device of claim 48, the trench isolation has an upper surface higher than the surface of the active area.

50. The semiconductor device of claim 48, wherein a lower portion of the interconnection provided on the upper surface of the trench isolation is located higher than the surface of the active area.

51. The semiconductor device of claim 44, wherein the interconnection is composed of the same material as the gate electrode.

52. The semiconductor device of claim 51, wherein the gate electrode and the interconnection has at least a polysilicon film.