Microelectronic device having disposable spacer

• US 20050121750A1
• Filed: 12/05/2003
• Published: 06/09/2005
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chan, Bor-Wen, Wang, Yu-I, Tao, Han-Jan
• Granted Patent: US 7,202,172 B2
• Time in Patent Office: Days
• US Class Current: 257/643
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Claims

1. A method of manufacturing a microelectronic device, comprising:

forming a patterned feature over a substrate;

depositing a conformal polymer layer over the patterned feature and the substrate, employing a fluorine-containing plasma source; and

etching the polymer layer to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

2. The method of claim 1 wherein the conformal polymer layer is deposited in a chemical reactive plasma environment.

3. The method of claim 1 wherein the substrate comprises diamond.

4. The method of claim 1 wherein the substrate comprises strained silicon.

5. The method of claim 1 wherein the patterned feature is a semiconductor device gate structure.

6. The method of claim 1 wherein the fluorine-containing chemistry comprises CF₄.

7. The method of claim 1 wherein the fluorine-containing chemistry comprises CF₃.

8. The method of claim 1 wherein the fluorine-containing chemistry comprises C₂F₂.

9. The method of claim 1 wherein the fluorine-containing chemistry comprises CH₂F₂.

10. The method of claim 1 wherein the fluorine-containing chemistry comprises CHF₃.

11. The method of claim 1 wherein the fluorine-containing chemistry comprises C₂F₆.

12. The method of claim 1 wherein the fluorine-containing chemistry comprises C₃F₈.

13. The method of claim 1 wherein the fluorine-containing chemistry comprises SF₆.

14. The method of claim 1 wherein the fluorine-containing chemistry comprises C₃F.

15. The method of claim 1 wherein the fluorine-containing chemistry comprises CH₃F.

16. The method of claim 1 wherein the fluorine-containing chemistry comprises a fluorocarbon.

17. The method of claim 1 wherein a flow rate of the fluorine-containing chemistry ranges between about 5 sccm and about 200 sccm.

18. The method of claim 1 wherein the fluorine-containing chemistry further includes a chlorine-containing gas.

19. The method of claim 18 wherein the chlorine-containing gas comprises Cl₂ and chlorocarbons.

20. The method of claim 1 wherein the fluorine-containing chemistry further includes a bromine-containing gas.

21. The method of claim 20 wherein the bromine-containing gas comprises HBr.

22. The method of claim 1 wherein the etching employs an oxygen-containing gas.

23. The method of claim 22 wherein the oxygen-containing gas comprises O₂.

24. The method of claim 22 wherein the oxygen-containing gas comprises O₃.

25. The method of claim 22 wherein the oxygen-containing gas comprises NO₂.

26. The method of claim 22 wherein the oxygen-containing gas comprises CO₂.

27. The method of claim 22 wherein the oxygen-containing gas comprises CO.

28. The method of claim 1 wherein depositing the polymer layer employs a direct current (DC) bias applied to the substrate ranging between about 1 Watts and about 50 Watts.

29. The method of claim 1 wherein depositing the polymer layer employs a radio frequency (RF) bias applied to the substrate ranging between about 1 Watts and about 50 Watts.

30. The method of claim 1 wherein the etching the spacer employs a direct current (DC) bias applied to the substrate ranging between about 1 Watts and about 500 Watts.

31. The method of claim 1 wherein the etching the spacer employs a radio frequency (RF) bias applied to the substrate ranging between about 1 Watts and about 500 Watts.

32. The method of claim 1 further comprising:

forming source/drain regions in the substrate on opposing sides of the patterned feature; and

removing the spacers after forming the source/drain regions.

33. The method of claim 32 wherein removing the spacers includes etching the spacers with an oxygen-containing gas.

34. A microelectronic device, comprising:

a substrate;

a patterned feature located over the substrate;

polymer spacers containing fluorine and located on opposing sides of the patterned feature.

35. The microelectronic device of claim 34 herein the polymer spacers have a thickness ranging between about 5 Angstroms and about 1000 Angstroms.

36. A integrated circuit device, comprising:

a substrate;

a plurality of microelectronic devices each comprising;

a patterned feature located over the substrate; and

polymer spacers containing fluorine and located on opposing sides of the patterned feature; and

at least one interconnect electrically connecting ones of the plurality of microelectronic devices.