Microelectronic device having disposable spacer

• US 7,202,172 B2
• Filed: 12/05/2003
• Issued: 04/10/2007
• Est. Priority Date: 12/05/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chan, Bor-Wen, Wang, Yu-I, Tao, Han-Jan
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US10/728,995
• Publication Number:
  US 20050121750A1
• Time in Patent Office: 1,222 Days
• Field of Search: 438/303, 438/301, 438/595, 438694-696, 438/725, 438/780
• US Class Current: 438/694
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Claims

1. A method of manufacturing a microelectronic device, comprising:

forming a patterned feature on a substrate;

depositing a conformal polymer layer on the patterned feature and the substrate, wherein such depositing employs a fluorine-containing plasma source;

etching the polymer layer to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature; and

forming an insulating layer on the polymer spacers.

2. The method of claim 1 wherein the conformal polymer layer is deposited in a chemical reactive plasma environment.

3. The method of claim 1 wherein the substrate comprises diamond.

4. The method of claim 1 wherein the substrate comprises strained silicon.

5. The method of claim 1 wherein the patterned feature is a semiconductor device gate structure.

6. The method of claim 1 wherein the fluorine-containing plasma source comprises CF₄.

7. The method of claim 1 wherein the fluorine-containing plasma source comprises CF₃.

8. The method of claim 1 wherein the fluorine-containing plasma source comprises C₂F₂.

9. The method of claim 1 wherein the fluorine-containing plasma source comprises CH₂F₂.

10. The method of claim 1 wherein the fluorine-containing plasma source comprises CHF₃.

11. The method of claim 1 wherein the fluorine-containing plasma source comprises C₂F₆.

12. The method of claim 1 wherein the fluorine-containing plasma source comprises C₃F₈.

13. The method of claim 1 wherein the fluorine-containing plasma source comprises SF₆.

14. The method of claim 1 wherein the fluorine-containing plasma source comprises C₃F.

15. The method of claim 1 wherein the fluorine-containing plasma source comprises CH₃F.

16. The method of claim 1 wherein the fluorine-containing plasma source comprises a fluorocarbon.

17. The method of claim 1 wherein a flow rate of the fluorine-containing plasma source ranges between about 5 sccm and about 200 sccm.

18. The method of claim 1 wherein the fluorine-containing plasma source further includes a chlorine-containing gas.

19. The method of claim 18 wherein the chlorine-containing gas comprises Cl₂ and chlorocarbons.

20. The method of claim 1 wherein the fluorine-containing plasma source further includes a bromine-containing gas.

21. The method of claim 20 wherein the bromine-containing gas comprises HBr.

22. The method of claim 1 wherein the etching employs an oxygen-containing gas.

23. The method of claim 22 wherein the oxygen-containing gas comprises O₂.

24. The method of claim 22 wherein the oxygen-containing gas comprises O₃.

25. The method of claim 22 wherein the oxygen-containing gas comprises NO₂.

26. The method of claim 22 wherein the oxygen-containing gas comprises CO₂.

27. The method of claim 22 wherein the oxygen-containing gas comprises CO.

28. The method of claim 1 wherein the step of depositing the polymer layer employs a direct current (DC) bias applied to the substrate ranging between about 1 Watts and about 50 Watts.

29. The method of claim 1 wherein the step of depositing the polymer layer employs a radio frequency (RF) bias applied to the substrate ranging between about 1 Watts and about 50 Watts.

30. The method of claim 1 wherein the etching the spacer employs a direct current (DC) bias applied to the substrate ranging between about 1 Watts and about 500 Watts.

31. The method of claim 1 wherein the etching the spacer employs a radio frequency (RF) bias applied to the substrate ranging between about 1 Watts and about 500 Watts.

32. The method of claim 1 further comprising:

forming source/drain regions in the substrate on opposing sides of the patterned feature.

33. The method of claim 32 wherein removing the spacers includes etching the spacers with an oxygen-containing gas.

34. A method of manufacturing a microelectronic device, comprising:

forming a doped well in a substrate;

forming a gate stack over the doped well;

forming, in-situ, polymer spacers on opposing sides of the gate stack by;

employing a substrate bias and a fluorine-containing plasma source to deposit a conformal polymer layer over the gate stack; and

adjusting the substrate bias, without removing the substrate bias, to etch the polymer layer with the fluorine-containing plasma, thereby exposing the gate stack and defining the polymer spacers; and

forming an insulating layer over the polymer spacers.

35. The method of claim 34 wherein forming the doped well includes:

employing a high density plasma source to form the doped well, the high density plasma source having a carbon-to-deuterium ratio ranging between about 0.1 percent and about 5 percent in a process ambient, wherein the process ambient pressure ranges between about 0.1 mTorr and about 500 Torr and the substrate is held at a temperature ranging between about 150°

C. and about 1100°

C.; and

treating the doped well by employing a deuterium-containing plasma.

36. The method of claim 34 further comprising:

forming source/drain regions in the doped well via ion implantation before the step of forming the insulating layer, wherein forming the source/drain regions includes employing the polymer spacers to laterally limit formation of the source/drain regions during the ion implantation; and

forming contact regions over the source/drain regions and contacting the polymer spacers, before the step of forming the insulating layer.