METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A LOW K DIELECTRIC

• US 20050130405A1
• Filed: 12/16/2003
• Published: 06/16/2005
• Est. Priority Date: 12/16/2003
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Spencer, Gregory S., Turner, Michael D.
• Granted Patent: US 6,903,004 B1
• Time in Patent Office: Days
• US Class Current: 438/624
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K<3.0) overlying the substrate of the wafer, forming an organic silicon-oxide glue layer overlying the low K dielectric, and forming a CMP stop layer dielectric overlying the glue layer dielectric. A void is then formed in the ILD, a conductive material is deposited to fill the void, and a polish process removes the excess conductive material. Forming the glue layer dielectric and the CMP stop layer dielectric is achieved by forming a CVD plasma using an organic precursor and an oxygen precursor and maintaining the plasma through the formation of the glue layer dielectric and the stop layer. The flow rate of the organic precursor is reduced relative to the oxygen precursor flow rate to form a CMP stop layer that is substantially free of carbon.

Claims

1. A semiconductor fabrication process, comprising:

forming an interlevel dielectric (ILD) overlying a substrate of a semiconductor wafer wherein forming the ILD comprises;

forming a low K dielectric overlying a semiconductor substrate of the wafer, wherein a dielectric constant of the low K dielectric is less than or equal to 3.0;

forming an organic, silicon-oxide, glue layer dielectric overlying the low K dielectric; and

forming a CMP stop layer dielectric overlying the glue layer dielectric;

forming a void in the ILD;

depositing a conductive material over the wafer to fill the void; and

removing portions of the conductive material exterior to the void by polishing the wafer with a CMP process and terminating the CMP process on the CMP stop layer dielectric.

2. The method of claim 1, wherein forming the glue layer dielectric and the CMP stop layer dielectric comprises:

forming a plasma within a CVD reactor chamber using a specified set of precursors including a carbon bearing precursor and maintaining the plasma during formation of the glue layer dielectric; and

following formation of the glue layer dielectric, reducing a flow rate of the carbon bearing precursor while continuing to maintain the plasma to form the CMP stop layer dielectric wherein the CMP stop layer dielectric is substantially free of carbon.

3. The method of claim 2, wherein the specified set of precursors includes an oxygen bearing precursor and a second precursor selected from tetramethylsilane (4MS) and trimethylsilane (3MS).

4. The method of claim 3, wherein a ratio of the oxygen precursor flow rate to the second precursor flow rate is less than 1:

2 while forming the glue layer dielectric and further wherein the ratio exceeds 2;

1 while forming the CMP stop layer dielectric.

5. The method of claim 4, wherein the reactor chamber temperature and pressure are maintained at constant during the formation of the glue layer dielectric and the CMP stop layer dielectric.

6. The method of claim 2, wherein forming the low K dielectric comprises spinning on a low K material.

7. The method of claim 2, wherein forming the low K dielectric comprises depositing an OctaMethylCycloTetra Siloxane (OMCTS) material.

8. A method of forming an interlevel dielectric layer (ILD) overlying a substrate of a semiconductor wafer, comprising:

forming a first dielectric having a dielectric constant less than or equal to 3.0 overlying the substrate;

depositing, with a chemical vapor deposition process, second and third dielectrics overlying the first dielectric, wherein forming the second and third dielectrics comprises forming a plasma from an oxygen bearing precursor and an organic precursor, maintaining the flow rates of the precursors at first flow rates while forming the second dielectric, and thereafter, reducing the relative flow rate of the organic precursor while maintaining the plasma to form the third dielectric.

9. The method of claim 8, wherein forming the first dielectric comprises spinning on a silsesquioxane-based film.

10. The method of claim 8, wherein forming the first dielectric comprises depositing an OctaMethylCycloTetra Siloxane (OMCTS)-based film.

11. The method of claim 8, wherein the second dielectric comprises an organic silicon-oxide, and further wherein the third dielectric comprises substantially carbon-free silicon-oxide.

12. The method of claim 8, wherein the organic precursor comprises an precursor selected from 3MS and 4MS.

13. The method of claim 12, wherein a ratio of the oxygen precursor flow rate to the organic precursor flow rate is less than 1:

2 while forming the second dielectric and further wherein the ratio exceeds 2;

1 while forming the third dielectric.

14. The method of claim 13, wherein a temperature and pressure of a reactor chamber of the CVD process remain constant during formation of the second and third dielectrics and further wherein an radio frequency power of the reactor chamber is uninterrupted during formation of the second and third dielectrics.

15. A semiconductor fabrication process, comprising:

forming a first dielectric having a dielectric constant of less than or equal to 3.0 over a semiconductor substrate;

forming, in a chemical vapor deposition (CVD) reactor chamber using a continuously maintained plasma derived from an oxygen precursor and an organic precursor, a second dielectric overlying the first dielectric and a third dielectric overlying the second dielectric, wherein the second dielectric comprises an organic silicon-oxide and the third dielectric comprises a substantially carbon free silicon-oxide.

16. The method of claim 15, wherein forming the first dielectric comprises spin depositing a silsesquioxane-based material overlying the substrate.

17. The method of claim 15, wherein forming the first dielectric comprises depositing an OctaMethylCycloTetra Siloxane (OMCTS)-based film overlying the substrate.

18. The method of claim 15, wherein the organic precursor comprises 3MS or 4MS.

19. The method of claim 18, wherein the flow rate of the organic precursor exceeds the flow rate of the oxygen precursor while forming the second dielectric and the organic precursor flow rate is less than the oxygen precursor flow rate during while forming the third dielectric.

20. The method of claim 19, wherein the CVD reactor temperature and pressure are maintained at constant values during formation of the second and third dielectrics.