Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same
First Claim
1. A semiconductor memory device, comprising:
- a substrate;
a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;
a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in said semiconductor layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;
an impurity-diffused region of said first conductive type formed at a location in contact with the upper surface of said drain region, said impurity-diffused region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region; and
a write transistor including a bipolar transistor having said impurity-diffused region as an emitter region, said drain region as a base region and said channel body as a collector region, said write transistor operative to write data in said memory transistor.
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Accused Products
Abstract
A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.
211 Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a substrate;
a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;
a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in said semiconductor layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;
an impurity-diffused region of said first conductive type formed at a location in contact with the upper surface of said drain region, said impurity-diffused region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region; and
a write transistor including a bipolar transistor having said impurity-diffused region as an emitter region, said drain region as a base region and said channel body as a collector region, said write transistor operative to write data in said memory transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor memory device, comprising:
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a substrate;
a semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;
a plurality of memory transistors, each having a gate electrode, a pair of impurity regions of a second conductive type formed in said semiconductor layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;
an interlayer insulator film formed to cover said plurality of memory transistors; and
a conductive plug shared by memory transistors in which one of said pair of impurity regions being adjacent each other among said plurality of memory transistors, formed in and projected through said interlayer insulator film, and buried in one of said pair of impurity regions. - View Dependent Claims (14, 15)
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16. A method of manufacturing a semiconductor memory device, comprising:
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forming a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions;
forming an interlayer insulator film to cover said memory transistor;
forming an emitter contact hole in said interlayer insulator film to expose said drain region;
forming an emitter plug of said first conductive type in said emitter contact hole; and
forming an emitter region of said first conductive type in the upper surface of said drain region by thermally diffusing an impurity of said first conductive type from inside said emitter plug to the upper surface of said drain region, said emitter region having a higher impurity concentration of said first conductive type than an impurity concentration of said second conductive type in said drain region. - View Dependent Claims (17, 18)
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19. A method of manufacturing a semiconductor memory device, comprising:
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forming a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions;
forming an interlayer insulator film to cover said memory transistor;
forming an emitter contact hole in said interlayer insulator film to expose said drain region; and
forming a single crystalline layer of said first conductive type serving as an emitter region in said emitter contact hole by selective epitaxial growth.
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20. A method of manufacturing a semiconductor memory device, comprising:
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forming a plurality of memory transistors, each having a gate electrode, a pair of impurity regions of a second conductive type formed in a semiconductor layer of a first conductive type isolated from a substrate by an insulator layer, and a channel body of said first conductive type formed in said semiconductor layer between said regions, in which adjacent memory transistors share one of said pair of impurity regions;
forming an interlayer insulator film to cover said plurality of memory transistors;
forming a contact hole in said interlayer insulator film as entering inside one of said pair of impurity regions; and
forming a conductive plug in said contact hole as entering inside one of said pair of impurity regions and as being shared by adjacent memory transistors.
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Specification