Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

• US 7,301,195 B2
• Filed: 11/23/2004
• Issued: 11/27/2007
• Est. Priority Date: 02/02/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakajima, Hiroomi, Inoh, Kazumi
• Primary Examiner(s): Pham; Long
• Application Number:
  US10/994,629
• Publication Number:
  US 20050167751A1
• Time in Patent Office: 1,099 Days
• Field of Search: 257/315, 257/314, 257/316
• US Class Current: 257/315
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.

Claims

1. A semiconductor memory device, comprising:

a substrate;

semiconductor layer of a first conductive type isolated from said substrate by an insulator layer;

a plurality of memory transistors, each having

a gate electrode,

a pair of impurity regions of a second conductive type formed in said semiconductor layer, and

a channel body of said first conductive type formed in said semiconductor layer between said regions, said memory transistor operative to store data as a state of majority carriers accumulated in said channel body;

an interlayer insulator film formed to cover said plurality of memory transistors; and

a conductive plug shared by memory transistors in which one of said pair of impurity regions being adjacent each other among said plurality of memory transistors, formed in and projected through said interlayer insulator film, and buried in one of said pair of impurity regions.

2. The semiconductor memory device according claim 1, wherein said plug reaches said insulator layer.

3. The semiconductor memory device according claim 1, wherein said plug contains polysilicon of said second conductive type.