Flash memory system with a high-speed flash controller

• US 20050223158A1
• Filed: 04/05/2004
• Published: 10/06/2005
• Est. Priority Date: 04/05/2004
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Technology, Corporation
• Inventors: Lee, Charles C., Chou, Horng-Yee, Chu, Tzu-Yih, See, Sun-Teck
• Granted Patent: US 7,243,185 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port

Abstract

A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

Claims

1. A multi media card (MMC) comprising:

a flash controller; and

at least one flash memory device, wherein the flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC.

2. The MMC of claim 1 wherein the flash controller increases the throughput by performing a read-ahead memory read operation.

3. The MMC of claim 1 wherein the flash controller increases the throughput by performing a write-ahead memory write operation.

4. The MMC of claim 1 wherein the throughput is increased by increasing the size of a page register of the at least one flash memory device such that a greater number of bytes per second can be transmitted through the host bus.

5. The MMC of claim 4 wherein the page register is increased to at least 2048 bytes such that a greater number of bytes per second can be transmitted through the host bus.

6. The MMC of claim 1 further comprising a memory data bus, wherein the throughput is increased by increasing the width of the memory data bus such that a greater number of bytes per second can be transmitted through the host bus.

7. The MMC of claim 6 wherein the width of the memory data bus in increased to at least 16 bits such that a greater number of bytes per second can be transmitted through the host bus.

8. The MMC of claim 1 wherein the throughput is increased by performing a dual-channel concurrent memory read operation and/or a dual-channel concurrent memory write operation.

9. The MMC of claim 1 wherein the throughput is increased by performing a write-cache memory write operation.

10. The MMC of claim 1 wherein the throughput is increased by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device such that a greater number of bytes per second can be transmitted through the host bus, increasing the width of a memory data bus such that a greater number of bytes per second can be transmitted through the host bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing write-cache memory write operation, and any combination thereof.

11. The MMC of claim 10 wherein the page register is increased to at least 2048 bytes such that a greater number of bytes per second can be transmitted through the host bus.

12. The MMC of claim 10 wherein the width of the memory data bus is increased to at least 16 bits such that a greater number of bytes per second can be transmitted through the host bus.

13. The MMC of claim 1 wherein the flash controller supports the host with different data widths, including but not limited to 1 bit, 4 bits, and 8 bits.

14. The MMC of claim 1 wherein the flash controller supports single-level cell (SLC) and multi-level cell (MLC) flash memories.

15. The MMC of claim 1 wherein the flash controller can be applied to flash memory devices comprising Secure Digital Card, Memory Stick Card, Compact Flash Card, USB Flash Drive, USB Flash Drive in Express Card mechanical form factor, PCI Express Drive in Express Card mechanical form factor.

16. The MMC of claim 1 wherein the flash controller can be applied to a variety of mass storage devices such as Serial ATA Flash hard drive, IDE Flash hard drive, SCSI Flash hard drive, and Ethernet Flash hard drive.

17. A flash memory system comprising:

a host bus;

a flash controller coupled to the host bus; and

at least one flash memory device, wherein the flash controller increases the throughput of the at least one flash memory device to match the speed of the host bus, wherein the throughput is increased by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

18. The system of claim 17 wherein the page register is increased to at least 2048 bytes such that a greater number of bytes per second can be transmitted through the host bus.

19. The system of claim 17 wherein the width of the memory data bus is increased to at least 16 bits such that a greater number of bytes per second can be transmitted through the host bus.

20. The system of claim 17 wherein the flash controller supports the host with different data widths, including but not limited to 1 bit, 4 bits, and 8 bits.

21. The system of claim 17 wherein the flash controller supports single-level cell (SLC) and multi-level cell (MLC) flash memories.

22. The system of claim 17 wherein the flash controller can be applied to flash memory devices comprising Secure Digital Card, Memory Stick Card, Compact Flash Card, USB Flash Drive, USB Flash Drive in Express Card mechanical form factor, PCI Express Drive in Express Card mechanical form factor.

23. The system of claim 17 wherein the flash controller can be applied to a variety of mass storage devices such as Serial ATA Flash hard drive, IDE Flash hard drive, SCSI Flash hard drive, and Ethernet Flash hard drive.