Flash memory system with a high-speed flash controller

• US 7,243,185 B2
• Filed: 04/05/2004
• Issued: 07/10/2007
• Est. Priority Date: 04/05/2004
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Lee, Charles C., Chou, Horng-Yee, Chu, Tzu-Yih, See, Sun-Teck
• Primary Examiner(s): Elmore; Stephen C.
• Application Number:
  US10/818,653
• Publication Number:
  US 20050223158A1
• Time in Patent Office: 1,191 Days
• Field of Search: 711/103, 711/154, 711/158, 711/167, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port

Abstract

A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

Claims

1. A multi media card (MMC) for use with a host device by way of a host bus having a predetermined speed, the MMC comprising:

a card body having a plurality of pins disposed along an edge thereof for electrical connection to the host bus;

a flash controller coupled to the plurality of pins; and

at least one flash memory device coupled to the flash controller by way of an internal bus,

wherein the flash controller comprises means for increasing a throughput of the at least one flash memory device to match the predetermined speed of a the host bus.

2. The MMC of claim 1 wherein the flash controller comprises means for performing a read-ahead memory read operation.

3. The MMC of claim 1 wherein the flash controller comprises means for performing a write-ahead memory write operation.

4. The MMC of claim 1,

wherein the at least one flash memory device includes a page register having a size of at least 2048 bytes, and

wherein the flash controller comprises means for increasing the throughput by matching the number of bytes per second transmitted between the host bus and the page register.

5. The MMC of claim 4 wherein the page register is one of 2048 bytes, 4096 bytes and 8192 bytes.

6. The MMC of claim 1,

wherein the internal bus includes a memory data bus having a width of at least 16 bits, and

wherein flash controller comprises means for increasing the throughput by matching the number of bits transmitted during each instance with the width of the memory data bus such that a greater number of bytes per second is transmitted between the host bus and the page register.

7. The MMC of claim 6 wherein the width of the memory data bus is one of 16 bits, 32 bits and 64 bits.

8. The MMC of claim 1 wherein the means for increasing throughput comprises means for performing at least one of a dual-channel concurrent memory read operation and a dual-channel concurrent memory write operation.

9. The MMC of claim 1 wherein the means for increasing throughput comprises means for performing a write-cache memory write operation.

10. The MMC of claim 1 wherein the means for increasing throughput comprises one or more of means for performing a read-ahead memory read operation, means for performing a write-ahead memory write operation, means for performing a dual-channel concurrent memory read operation, means for performing a dual-channel concurrent memory write operation, and means for performing write-cache memory write operation.

11. The MMC of claim 10 further comprising a page register having at least 2048 bytes, wherein said means for increasing throughput comprises means for transferring said at least 2048 bytes from the page register to the at least one flash memory device during a flash write data time, and means for transferring said at least 2048 bytes to the page register from the at least one flash memory device during a flash read data time.

12. The MMC of claim 10 wherein the internal bus includes a memory data bus having a width of at least 16 bits, and wherein said means for increasing throughput comprises means for simultaneously transferring at least 16 bits from the flash controller to the at least one flash memory device during a flash write data time, and means for simultaneously transferring at least 16 bits from the at least one flash memory device to the flash controller during a flash read data time.

13. The MMC of claim 1 wherein the flash controller supports the host bus with different data widths, including but not limited to 1 bit, 4 bits, and 8 bits.

14. The MMC of claim 1 wherein the flash controller comprises means for communicating with single-level cell (SLC) and multi-level cell (MLC) flash memories.

15. A flash memory system comprising:

a host bus;

a flash controller coupled to the host bus; and

at least one flash memory device, wherein the flash controller comprises one or more of means for performing a read-ahead memory read operation, means for performing a write-ahead memory write operation, means for performing a dual-channel concurrent memory read operation, means for performing a dual-channel concurrent memory write operation, and means for performing a write-cache memory write operation.

16. The system of claim 15 wherein the page register comprises at least 2048 bytes.

17. The system of claim 15 wherein the flash controller supports the host bus with different data widths, including but not limited to 1 bit, 4 bits, and 8 bits.

18. The system of claim 15 wherein the flash controller comprises means for communicating with single-level cell (SLC) and multi-level cell (MLC) flash memories.

19. The system of claim 15, wherein the system comprises one of a Secure Digital Card, a Memory Stick Card, a Compact Flash Card, an USB Flash Drive, an USB Flash Drive in Express Card mechanical form factor, and a PCI Express Drive in Express Card mechanical form factor.

20. The system of claim 15 wherein the system comprises one of a Serial ATA Flash hard drive, an IDE Flash hard drive, a SCSI Flash hard drive, and an Ethernet Flash hard drive.