High dynamic range pixel amplifier

• US 20050224843A1
• Filed: 04/07/2004
• Published: 10/13/2005
• Est. Priority Date: 04/07/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Boemler, Christian
• Granted Patent: US 7,091,531 B2
• Time in Patent Office: Days
• US Class Current: 257/233
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

Claims

1. A pixel cell comprising:

a photosensor;

a floating diffusion region for receiving charges from said photosensor; and

at least one gate coupled to said floating diffusion region and having an intrinsic capacitance, said at least one gate being selectively operable to change the capacitance of said floating diffusion region.

2. The pixel cell of claim 1, wherein said photosensor is selected from the group consisting of a photodiode, photogate, and photoconductor.

3. The pixel cell of claim 1, wherein a first readout of said floating diffusion region at a first floating diffusion capacitance is a low sensitivity readout, where the intrinsic capacitance of said at least one gate is added to said capacitance of said floating diffusion region when said at least one gate is on.

4. The pixel cell of claim 1, wherein a second readout of said floating diffusion region at a second floating diffusion capacitance is a high sensitivity readout, where the intrinsic capacitance of said at least one gate is removed from said capacitance of said floating diffusion region when said at least one gate is off.

5. The pixel cell of claim 1, further comprising a circuit for receiving a first pixel output signal generated by said first readout and a second pixel output signal generated by said second readout and combining said first and second pixel output signals to provide a single pixel signal.

6. The pixel cell of claim 1, wherein a portion of the intrinsic capacitance of said at least one gate is added to said capacitance of said floating diffusion region.

7. The pixel cell of claim 6, wherein a single readout is taken after the at least one gate has been selectively changed to add said portion of its intrinsic capacitance to said capacitance of said floating diffusion region.

8. The pixel cell of claim 1, wherein said gate has a commonly connected source/drain region.

9. The pixel cell of claim 8, wherein said source/drain region is in electrical communication with said floating diffusion region.

10. A pixel cell comprising:

a photosensor;

a switch having a gate structure and a commonly connected source/drain region; and

a floating diffusion region for receiving charges collected by said photosensor during a charge integration period, said commonly connected source/drain region of said switch being in electrical communication with said floating diffusion region.

11. The pixel cell of claim 10, wherein said photosensor is selected from the group consisting of a photodiode, photogate, and photoconductor.

12. The pixel cell of claim 11, further comprising a circuit for selectively operating said switch by applying a first voltage to said gate structure.

13. The pixel cell of claim 12, wherein said circuit for selectively operating said switch further applies a second voltage to said gate circuit, which is lower than said first voltage.

14. The pixel cell of claim 13, wherein said second voltage is approximately midway between said first voltage and a voltage that disables the switch.

15. The pixel cell of claim 13, further comprising a first readout circuit for obtaining a first pixel output signal taken when said switch is switched on and a second pixel output signal taken when said switch is switched off.

16. The pixel cell of claim 15, wherein said first and second pixel output signals are generated from the charges collected during a same charge integration period of said photosensor.

17. The pixel cell of claim 15, wherein said switch increases a capacitance of said floating diffusion region when switched on.

18. The pixel cell of claim 15, wherein said switch boosts a charge on said floating diffusion region when said switch is turned off.

19. The pixel cell of claim 15, further comprising a circuit for receiving said first and second pixel output signals and combining said first and second pixel output signals to provide a single pixel signal.

20. The pixel cell of claim 14, wherein a portion of an intrinsic capacitance of said switch is added to a capacitance of said floating diffusion region when said second voltage is applied to said switch.

21. The pixel cell of claim 20, wherein a conversion gain of said pixel cell decreases when said second voltage is applied to said switch.

22. A pixel cell comprising:

a photosensor; and

a floating diffusion region for receiving charges integrated by said photosensor during an integration period;

at least a first gate structure provided adjacent to said floating diffusion region for selectively changing the capacitance of said floating diffusion region.

23. The pixel cell of claim 22, wherein at least said first gate structure has an intrinsic capacitance.

24. The pixel cell of claim 23, wherein the capacitance of said floating diffusion region changes in a single integration period.

25. The pixel cell of claim 24, wherein at least said first gate structure increases said variable capacitance of said floating diffusion region by adding at least a portion of the intrinsic capacitance of at least said first gate structure to said capacitance of said floating diffusion region.

26. The pixel cell of claim 25, wherein a first voltage is applied to at least said first gate structure to turn at least said first gate structure on at a first portion of said single integration period.

27. The pixel cell of claim 26, wherein a second voltage, which is lower than the first voltage, is applied to at least partly turn at least said first gate structure off at a second portion of said single integration period.

28. The pixel cell of claim 27, wherein at least said first gate structure decreases said capacitance of said floating diffusion region by removing at least a portion of said intrinsic capacitance of at least said first gate structure from said capacitance of said floating diffusion region.

29. The pixel cell of claim 27, wherein said second voltage is set to completely turn said gate structure off.

30. The pixel cell of claim 29, wherein a first pixel output signal is taken during said first portion of said single integration period and a second pixel output signal is taken during said second portion of said single integration period.

31. The pixel cell of claim 30, wherein said first and second pixel output signals are combined to provide a single pixel output signal.

32. The pixel cell of claim 27, wherein said second voltage is approximately midway between said first voltage and a voltage that disables at least said first gate structure.

33. The pixel cell of claim 32, wherein a pixel output signal is taken during said second portion of said single integration period.

34. The pixel cell of claim 27, wherein said first voltage is applied to at least a second gate structure having an intrinsic capacitance to turn at least said second gate structure on at said first portion of said single integration period.

35. The pixel cell of claim 34, wherein a third voltage, which is lower than the second voltage, is applied to at least partly turn at least said second gate structure off at a second portion of said single integration period.

36. The pixel cell of claim 35, wherein at least said first and second gate structure decrease said capacitance of said floating diffusion region by removing at least a portion of the capacitances of at least said first and second gate structures from said capacitance of said floating diffusion region.

37. The pixel cell of claim 36, wherein a pixel output signal is taken during said second portion of said single integration period.

38. A pixel cell comprising:

a photosensor;

a floating diffusion region for receiving charges from said photosensor; and

a first gate coupled to said floating diffusion region, operable to provide a variable conversion gain to a pixel output signal in a readout period in accordance with a switched state of said first gate.

39. The pixel cell of claim 38, wherein said first gate provides a low conversion gain when said first gate is on by adding an intrinsic capacitance of said gate to a capacitance of said floating diffusion region.

40. The pixel cell of claim 39, wherein said first gate provides a high conversion gain when said gate is off and said intrinsic capacitance of said first gate is not combined with said capacitance of said floating diffusion region.

41. The pixel cell of claim 39, wherein said first gate provides a high conversion gain when a voltage is applied to said first gate and a portion of said intrinsic capacitance of said first gate is added to said capacitance of said floating diffusion region, wherein said voltage is approximately midway between said first voltage and ground.

42. The pixel cell of claim 38 further comprising at least a second gate coupled to said first gate and said floating diffusion region, wherein said first and at least said second gates provide a low conversion gain when said first and at least said second gates are on by adding intrinsic capacitances of said gates to a capacitance of said floating diffusion region.

43. The pixel cell of claim 42, wherein said first and at least said second gates provide a high conversion gain when a first voltage is applied to said first gate such that a portion of said intrinsic capacitance of said first gate is added to said capacitance of said floating diffusion region and a second voltage is applied to at least said second gate such that a portion of said intrinsic capacitance of at least said second gate is added to said capacitance of said floating diffusion region, wherein said second voltage is between said first voltage and ground.

44. An imager system, comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising;

a pixel array, each pixel in the pixel array comprising;

a photosensor;

a floating diffusion region for receiving charges from said photosensor; and

at least a first gate coupled to said floating diffusion region, operable to provide a variable conversion gain to a pixel output signal in a readout period in accordance with a switched state of at least said first gate.

45. The imager system of claim 44, wherein said pixel array is a CMOS pixel array.

46. The imager system of claim 44, wherein said pixel array is a CCD pixel array.

47. The imager system of claim 44, wherein at least said first gate provides a low conversion gain when a first voltage is applied to at least said first gate by adding an intrinsic capacitance of at least said first gate to a capacitance of said floating diffusion region.

48. The imager system of claim 47, wherein said at least said first gate provides a high conversion gain when at least said first gate is off and said intrinsic capacitance of at least said first gate is not combined with said capacitance of said floating diffusion region.

49. The imager system of claim 47, wherein at least said first gate provides a high conversion gain when at least a second voltage is applied to at least said first gate, wherein said second voltage is between said first voltage and ground.

50. A method of fabricating a pixel cell, comprising:

forming a photosensor on a substrate;

forming a floating diffusion region on said substrate; and

forming a gate capacitor over said substrate having a source and a drain region, said source and drain region of said gate capacitor being commonly connected to said floating diffusion region.

51. The method of claim 50, wherein at least a portion of a gate of said gate capacitor is formed adjacent to said floating diffusion region.

52. The method of claim 51 further comprising connecting a voltage source to said gate of said gate capacitor for operating said gate capacitor.

53. A method of operating a pixel cell, comprising:

generating charges with a photosensor during an integration period;

turning on a gate coupled to a storage node, said gate having intrinsic capacitance;

transferring charges from said photosensor to said storage node;

providing a first pixel output signal based on charges at said storage node with said gate on;

turning said gate off; and

taking a second pixel output signal based on charges at said storage node when said gate is off.

54. The method of claim 53, wherein said step of transferring charges from said photosensor removes substantially all charge from said photosensor.

55. The method of claim 53, wherein said step of turning said gate off boosts charges in said storage node.

56. The method of claim 53 further comprising combining said first and second pixel output signals to produce a combined pixel output signal.

57. The method of claim 56, wherein said first and second pixel output signals are generated from charges in a single photosensor integration period.

58. A method of operating a pixel cell, comprising:

generating charges with a photosensor during an integration period;

increasing a storage capacity of a storage node connected to said photosensor;

transferring charges from said photosensor to said storage node; and

selectively decreasing said storage capacity of said storage node.

59. The method of claim 58, wherein said step of transferring charges from said photosensor removes substantially all charge from said photosensor.

60. The method of claim 58 further comprising providing a first pixel output signal based on charges at said storage node after transferring charges from said photosensor.

61. The method of claim 60 further comprising taking a second pixel output signal based on charges at said storage node after selectively decreasing said storage capacity of said storage node.

62. The method of claim 61, wherein said storage capacity of said storage node is selectively decreased by decreasing a voltage applied to a gate coupled to said storage node.

63. The method of claim 62, wherein said gate is turned off to decrease said storage capacity of said storage node.

64. The method of claim 63 further comprising combining said first and second output signals to produce a combined pixel output signal.

65. The method of claim 58, wherein a knee is created in a charge-voltage graph of said pixel cell.

66. The method of claim 65 further comprising taking a reading after selectively decreasing said storage capacity of said storage node and calculating an output signal based on said knee.

67. A pixel cell comprising at least one gate at least partially adjacent to a floating diffusion region and selectively operable to change the charge to voltage relationship for an output signal of said pixel cell.

68. The pixel cell of claim 67, wherein said pixel cell comprises at least a first gate and a second gate.

69. The pixel cell of claim 68, wherein the charge to voltage relationship for said output signal changes in a single integration period.

70. The pixel cell of claim 68, wherein at least said first gate is turned on during a first portion of said integration period.

71. The pixel cell of claim 70, wherein at least said first gate is turned off during a second portion of said integration period.

72. The pixel cell of claim 70, wherein said first gate is turned off and said second gate is turned to a mid-level during a second portion of said integration period.

73. The pixel cell of claim 68, wherein said first gate is turned to a first level between on and off and said second gate is turned to a second level between said first level and off.

74. A pixel cell comprising at least one gate at least partially adjacent to a floating diffusion region, and obtaining Vrst, Vsig1, and Vsig2 from said pixel cell, wherein Vsig1 is taken when said at least one gate is in a first state, and Vsig2 is taken when said at least one gate is in a second state.

75. The pixel cell of claim 74, wherein the output signal is read out as a combination of Vrst, Vsig1, and Vsig2.

76. The pixel cell of claim 75, wherein the output signal is read out as Vrst−

(Vsig1+Vsig2)/2.

77. The pixel cell of claim 75, wherein the output signal is read out as Vrst-Vsig1.

78. The pixel cell of claim 75, wherein the output signal is read out as Vrst-Vsig2.

79. The pixel cell of claim 75, wherein the output signal is read out as Vsig1.

80. The pixel cell of claim 75, wherein the output signal is read out as Vsig2.

81. The pixel cell of claim 75, wherein one of Vsig1 and Vsig2 is selected for providing the output signal to read out as (Vrst-Vsig1) or (Vrst-Vsig2).