High dynamic range pixel amplifier

• US 7,091,531 B2
• Filed: 04/07/2004
• Issued: 08/15/2006
• Est. Priority Date: 04/07/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Boemler, Christian
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/819,167
• Publication Number:
  US 20050224843A1
• Time in Patent Office: 860 Days
• Field of Search: 257/222, 257/223, 257/225, 257/229, 257/239, 257/532, 438/60, 438/75, 438/78, 348/308
• US Class Current: 257/222
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

Claims

1. A pixel cell comprising:

a photosensor;

a floating diffusion region for receiving and storing charges from said photosensor;

at least one gate coupled to said floating diffusion region and having an intrinsic capacitance, said at least one gate being selectively operable to change the capacitance of said floating diffusion region; and

a readout circuit for providing at least two pixel output signals corresponding to charges stored at said floating diffusion during at least two different operative states of said at least one gate.

2. The pixel cell of claim 1, wherein said photosensor is selected from the group consisting of a photodiode, photogate, and photoconductor.

3. The pixel cell of claim 1, wherein said readout circuit provides a first pixel output signal as a low sensitivity output signal, where the intrinsic capacitance of said at least one gate is added to said capacitance of said floating diffusion region at a first operative state of said at least one gate, when said at least one gate is on.

4. The pixel cell of claim 3, wherein said readout circuit provides a second pixel output signal as a high sensitivity output signal, where the intrinsic capacitance of said at least one gate is removed from said capacitance of said floating diffusion region at a second operative state of said at least one gate when said at least one gate is off.

5. The pixel cell of claim 4, wherein said pixel cell is coupled to a pixel signal processing circuit which combines said first and second pixel output signals to provide a single pixel signal.

6. The pixel cell of claim 1, wherein at least a portion of the intrinsic capacitance of said at least one gate is selectively added to said capacitance of said floating diffusion region.

7. The pixel cell of claim 6, wherein a single pixel output signal is read out after the at least one gate has been selectively operated to add said portion of its intrinsic capacitance to said capacitance of said floating diffusion region.

8. The pixel cell of claim 1, wherein said gate has a commonly connected source/drain region in electrical communication with said floating diffusion region.

9. A pixel cell comprising:

a photosensor for collecting charges during a charge integration period;

at least a first and second switch each having a gate structure and a commonly connected source/drain region;

a floating diffusion region for receiving charges collected by said photosensor during said charge integration period, said commonly connected source/drain region of said first and second switches being in electrical communication with said floating diffusion; and

a readout circuit for providing at least two pixel output signals corresponding to charges at said floating diffusion when said gate structures are in at least two different operative states.

10. The pixel cell of claim 9, wherein said photosensor is selected from the group consisting of a photodiode, photogate, and photoconductor.

11. The pixel cell of claim 9, further comprising a circuit for selectively operating said first switch by applying a first voltage to the gate structure of said first switch.

12. The pixel cell of claim 11, wherein said circuit for selectively operating further operates said second switch by applying a second voltage to the gate structure of said second switch, said second voltage being lower than said first voltage.

13. The pixel cell of claim 12, wherein said second voltage is approximately midway between said first voltage and a voltage that switches off said second switch.

14. The pixel cell of claim 9, wherein said readout circuit provides said first pixel output signal when said first and second switches are switched on and said second pixel output signal when said first and second switches are switched off.

16. The pixel cell of claim 9, wherein said first and second switches each increase a capacitance of said floating diffusion region when switched on.

17. The pixel cell of claim 14, wherein each said switch boosts a charge on said floating diffusion region when turned off.

18. The pixel cell of claim 14, wherein said pixel cell is coupled to a circuit for receiving said first and second pixel output signals and combining said first and second pixel output signals to provide a single pixel signal.

19. The pixel cell of claim 9, wherein at least a portion of an intrinsic capacitance of each said switch is added to a capacitance of said floating diffusion region when each said switch is turned on.

20. The pixel cell of claim 19, wherein a conversion gain of said pixel cell decreases when each said switch is turned on.

64. The pixel cell of claim 12, wherein said second voltage is approximately midway between said first voltage and a voltage that disables said second switch.

65. The pixel cell of claim 14, wherein said first and second pixel output signals are generated from the charges collected during a same charge integration period of said photosensor.

15. A pixel cell comprising:

a photosensor;

a switch having a gate structure and a commonly connected source/drain region;

a floating diffusion region for receiving charges collected by said photosensor during a charge integration period, said commonly connected source/drain region of said switch being in electrical communication with said floating diffusion region;

a circuit for selectively operating said switch by applying a first voltage to said gate structure, said circuit for selectively operating said switch further applying a second voltage to said gate circuit, which is lower than said first voltage; and

a first readout circuit for obtaining a first pixel output signal taken when said switch is switched on and a second pixel output signal taken when said switch is switched off,

wherein said first and second pixel output signals are generated from the charges collected during a same charge integration period of said photosensor.

21. A pixel cell comprising:

a photosensor for integrating charges during one integration period;

a floating diffusion region for receiving charges integrated by said photosensor during said one integration period;

at least a first gate structure having an intrinsic capacitance provided adjacent to said floating diffusion region for selectively changing the capacitance of said floating diffusion region, said at least first gate structure overlapping a portion of said floating diffusion region; and

a readout circuit coupled to said floating diffusion region for providing at least two pixel output signals from charges at said floating diffusion region for at least two different operative states of said at least first gate structure.

22. The pixel cell of claim 21, wherein said at least first gate structure increases a capacitance of said floating diffusion region in at least a first operative state of said at least first gate structure by adding at least a portion of the intrinsic capacitance of said at least first gate structure to said capacitance of said floating diffusion region.

23. The pixel cell of claim 22, wherein a first voltage is applied to said at least first gate structure to turn said at least first gate structure on as said first operative state of said at least first gate structure.

24. The pixel cell of claim 23, wherein a second voltage, which is lower than the first voltage, is applied to at least partly turn said at least first gate structure off as a second operative state of said at least first gate structure.

25. The pixel cell of claim 24, wherein said at least first gate structure decreases said capacitance of said floating diffusion region in at least said second operative state of said at least first gate structure by removing at least a portion of said intrinsic capacitance of said at least first gate structure from said capacitance of said floating diffusion region.

26. The pixel cell of claim 24, wherein said second operative state includes said second voltage being set to completely turn said at least first gate structure off.

29. The pixel cell of claim 24, wherein said second voltage is approximately midway between said first voltage and a voltage that disables said at least first gate structure.

30. The pixel cell of claim 24, wherein said first voltage is applied to a second gate structure having an intrinsic capacitance to turn said second gate structure on as a first operative state of said second gate structure.

31. The pixel cell of claim 30, wherein a third voltage, which is lower than the second voltage, to at least partly turn said second gate structure off as a second operative state of said second gate structure.

32. The pixel cell of claim 31, wherein said at least first and second gate structures decrease said capacitance of said floating diffusion region by removing at least a portion of the capacitances of said at least said first and second gate structures from said capacitance of said floating diffusion region.

27. A pixel cell comprising:

a photosensor for integrating charges during an integration period;

a floating diffusion region for receiving charges integrated by said photosensor during said integration period, said floating diffusion region having a capacitance;

at least a first gate structure provided at least partially over said floating diffusion region for selectively changing the capacitance of said floating diffusion region, wherein said at least first gate structure has an intrinsic capacitance;

wherein said at least first gate structure increases said capacitance of said floating diffusion region by adding at least a portion of the intrinsic capacitance of said at least first gate structure to said capacitance of said floating diffusion region;

a control signal source for applying a first voltage to said at least first gate structure to turn said at least first gate structure on during a first portion of a pixel readout period, and for applying a second voltage, which is lower than the first voltage, to completely turn said at least first gate structure off during a second portion of said pixel readout period; and

,

a readout circuit for providing a first pixel output signal during said first portion of said pixel readout period and a second pixel output signal during said second portion of said pixel readout period.

28. The pixel cell of claim 27, further comprising a circuit for combining said first and second pixel output signals to provide a single pixel output signal.

33. A pixel cell comprising:

a photosensor;

a floating diffusion region for receiving charges from said photosensor;

a first gate coupled to said floating diffusion region, operable to provide a variable conversion gain to a pixel output signal in a readout period in accordance with a switched state of said first gate; and

a readout circuit providing at least two output signals for said pixel during said readout period with respective associated conversion gains.

34. The pixel cell of claim 33, wherein said first gate provides a low conversion gain when said first gate is on by adding an intrinsic capacitance of said gate to a capacitance of said floating diffusion region.

35. The pixel cell of claim 34, wherein said first gate provides a high conversion gain when said gate is off and said intrinsic capacitance of said first gate is not combined with said capacitance of said floating diffusion region.

36. The pixel cell of claim 34, wherein said first gate provides a high conversion gain when a voltage is applied to said first gate and a portion of said intrinsic capacitance of said first gate is added to said capacitance of said floating diffusion region, wherein said voltage is between a first voltage and ground.

37. The pixel cell of claim 33 further comprising a second gate coupled to said floating diffusion region, wherein said first and second gates provide a low conversion gain when said first and second gates are on by adding intrinsic capacitances of said gates to a capacitance of said floating diffusion region.

38. A pixel cell comprising:

a photosensor;

a floating diffusion region for receiving charges from said photosensor;

a first gate coupled to said floating diffusion region, operable to charge a conversion gain to a pixel output signal of a readout period in accordance with a switched state of said first gate; and

a second gate coupled to said floating diffusion region operable to change a conversion gain in a readout period in accordance with a switched state of said second gate, wherein said first and second gates provide a low conversion gain when said first and second gates are on by adding intrinsic capacitances of said gates to a capacitance of said floating diffusion region;

wherein said first and second gates provide a high conversion gain when a first voltage is applied to said first gate such that a portion of said intrinsic capacitance of said first gate is added to said capacitance of said floating diffusion region and a second voltage is applied to said second gate such that a portion of said intrinsic capacitance of said second gate is added to said capacitance of said floating diffusion region, wherein said second voltage is between said first voltage and ground.

39. An imager system, comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising;

a pixel array, each pixel in the pixel array comprising;

a photosensor;

a floating diffusion region for receiving charges from said photosensor; and

at least a first gate coupled to said floating diffusion region, operable to provide respective conversion gain to at least two pixel output signal in an associated readout period in accordance with a switched state of at least said first gate.

40. The imager system of claim 39, wherein said at least first gate provides a low conversion gain when a first voltage is applied to said at least first gate by adding an intrinsic capacitance of said at least first gate to a capacitance of said floating diffusion region.

41. The imager system of claim 40, wherein said at least first gate provides a high conversion gain when said at least first gate is off and said intrinsic capacitance of at least said first gate is not combined with said capacitance of said floating diffusion region.

42. The imager system of claim 40, wherein said at least first gate provides a high conversion gain when a second voltage is applied to said at least first gate, wherein said second voltage is between said first voltage and ground.

43. A method of operating a pixel cell, comprising:

generating charges with a photosensor during an integration period;

turning on a gate coupled to a storage node, said gate having intrinsic capacitance;

transferring charges from said photosensor to said storage node;

providing a first pixel output signal based on charges at said storage node with said gate on;

turning said gate off; and

providing a second pixel output signal based on charges at said storage node when said gate is off.

44. The method of claim 43, wherein said step of transferring charges from said photosensor removes substantially all charge from said photosensor.

45. The method of claim 43, wherein said step of turning said gate off boosts charges in said storage node.

46. The method of claim 43 further comprising combining said first and second pixel output signals to produce a combined pixel output signal.

47. The method of claim 46, wherein said first and second pixel output signals are generated from charges generating a single photosensor integration period.

48. A method of operating a pixel cell, comprising:

generating charges with a photosensor during an integration period;

selectively increasing a storage capacity of a storage node connected to said photosensor;

transferring charges from said photosensor to said storage node;

selectively decreasing said storage capacity of said storage node;

providing a first pixel output signal during a pixel readout period based on charges at said storage node when said storage capacity is selectively increasing; and

providing a second pixel output signal during said pixel readout period when said storage capacity is selectively decreasing.

49. The method of claim 48, wherein said step of transferring charges from said photosensor removes substantially all charge from said photosensor.

50. The method of claim 48, wherein said storage capacity of said storage node is selectively decreased by decreasing a voltage applied to a gate coupled to said storage node.

51. The method of claim 50, wherein said gate is turned off to decrease said storage capacity of said storage node.

52. The method of claim 48 further comprising combining said first and second output signals to produce a combined pixel output signal.

53. The method of claim 48, wherein a knee is created in a charge-voltage graph of said pixel cell by said selective decreasing.

54. A pixel cell comprising:

a first and second gate, each at least partially over a floating diffusion region and selectively operable to change the charge to voltage relationship for an output signal of said pixel cell;

a control circuit for generating control signals to turn said first gate on during a first portion of a pixel readout period and for turning said first gate off and said second gate partially on during a second portion of said pixel readout period.

55. A pixel cell comprising:

a first and second gate, each at least partially over a floating diffusion region and selectively operable to change the charge to voltage relationship for an output signal of said pixel cell during a pixel readout period;

a control circuit for generating control signals such that said first gate is turned to a first level between on and off and said second gate is turned to a second level between said first level and off during said pixel readout period.

56. A pixel cell comprising at least one gate at least partially over a floating diffusion region;

and a readout circuit providing Vrst, Vsig1, and Vsig2 signals from said pixel cell, wherein Vsig1 is taken when said at least one gate is in a first state during a pixel readout period, and Vsig2 is taken when said at least one gate is in a second state during said pixel readout period.

57. The pixel cell of claim 56, wherein an output signal is produced as a combination of Vrst, Vsig1, and Vsig2.

58. The pixel cell of claim 57, wherein the output signal is produced as Vrst−

(Vsig1+Vsig2)/2.

59. The pixel cell of claim 57, wherein the output signal is produced as Vrst−

Vsig1.

60. The pixel cell of claim 57, wherein the output signal is produced as Vrst−

Vsig2.

61. The pixel cell of claim 57, wherein the output signal is produced as Vsig1.

62. The pixel cell of claim 57, wherein the output signal is produced as Vsig2.

63. The pixel cell of claim 57, wherein one of Vsig1 and Vsig2 is selected for providing the output signal which is produced as (Vrst−

Vsig1) or (Vrst−

Vsig2).