Memory control method for time deinterleaving in DMB receiver

• US 20050226354A1
• Filed: 04/07/2005
• Published: 10/13/2005
• Est. Priority Date: 04/09/2004
• Status: Abandoned Application

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Shin, Jong Woong, Kang, Ik-Seon
• Application Number:
  US11/100,574
• Publication Number:
  US 20050226354A1
• Time in Patent Office: Days
• US Class Current: 375/346
• CPC Class Codes: H03M 13/2732 Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
• CPC Class Codes: H03M 13/276 Interleaving address generation
• CPC Class Codes: H03M 13/2782 Interleaver implementations, which reduce the amount of required interleaving memory
• CPC Class Codes: H03M 13/2785 Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location
• CPC Class Codes: H04H 20/426 Receiver side
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

Provided is a method for controlling a memory for time deinterleaving in a DMB receive by using byte addressing. The memory control method includes the steps of constructing the memory by the several segments so as to store only sample data used for actual time deinterleaving during a time period corresponding to M+1 frames from a time point r through a time point r+M; storing a plurality of sample data at one memory address by accessing the memory on a segment basis through byte addressing; and generating a byte-based memory address according to a time deinterleaving rule determined by the i value, and reading one of the sample data stored at the memory address and masking and another sample data stored at the memory address according to what order sample data is to be read from the memory address, thereby making it possible to greatly reduce the complexity of a memory address decoder in the memory.

Claims

1. A method for controlling a memory of a DMB receiver receiving and time-deinterleaving sample data of respective frames time-interleaved according to i values generated by modulo M, the method comprising the steps of:

(a) constructing the memory by the several segments so as to store only sample data used for actual time deinterleaving during a time period corresponding to M+1 frames from a time point r through a time point r+M; and

(b) performing time deinterleaving on a segment basis by performing memory read/write access on the sample data according to a time deinterleaving rule determined by the i values.

2. The method of claim 1, wherein the memory has a byte-based address and M is 15.

3. The method of claim 1, wherein the memory is constructed by the 15 segments in the step (a) so as to store sample data of respective frame from i=0 through i=15, the sample data being time-deinterleaved during a 16-frame period from a time point M through a time point M+1.

4. The method of claim 1, wherein the number of sample data used for actual time deinterleaving during a 16-time period from a time point r through a time point r+15 is determined according to i values in the step (a).

5. The method of claim 1, wherein the size of each segment in the step (a) is changed according to the i values.

6. The method of claim 1, wherein the size of each segment in the step (a) is determined as an integer obtained by dividing the number of sample data by 2 and rounding off a decimal portion of the resulting operation value, the number of the sample data being determined by a corresponding i value.

7. The method of claim 1, wherein a segment is not assigned in the step (a) if i=15.

8. The method of claim 1, wherein the step (b) comprises the steps of:

storing a plurality of sample data at one memory address by accessing the memory on a segment basis through byte addressing; and

generating a byte-based memory address according to a time deinterleaving rule determined by the i value, and reading one of the sample data stored at the memory address and masking and another sample data stored at the memory address according to what order sample data is to be read from the memory address.

9. The method of claim 8, wherein the sample data is stored by taking modulo of a corresponding segment size with respect to sample data inputted on a segment basis.

10. A method for controlling a memory of a DMB receiver receiving and time-deinterleaving sample data of respective frames time-interleaved according to i values generated by modulo M, the method comprising the steps of:

constructing the memory by the several segments so as to store only sample data used for actual time deinterleaving during a time period corresponding to M+1 frames from a time point r through a time point r+M;

storing a plurality of sample data at one memory address by accessing the memory on a segment basis through byte addressing; and

generating a byte-based memory address according to a time deinterleaving rule determined by the i value, and reading one of the sample data stored at the memory address and masking and another sample data stored at the memory address according to what order sample data is to be read from the memory address.

11. The method of claim 10, wherein the memory has a byte-based address and M is 15.

12. The method of claim 11, wherein the memory is constructed by the 15 segments in the step of constructing the memory so as to store sample data of respective frame from i=0 through i=15, the sample data being time-deinterleaved during a 16-frame period from a time point M through a time point M+1, the size of each segment being changed according to the i values.

13. The method of claim 12, wherein the number of sample data used for actual time deinterleaving during a 16-time period from a time point r through a time point r+15 is determined according to i values in the step of constructing the memory.

14. The method of claim 13, wherein the size of each segment in the step of constructing the memory is determined as an integer obtained by dividing the number of sample data by 2 and rounding off a decimal portion of the resulting operation value, the number of the sample data being determined by a corresponding i value.

15. The method of claim 13, wherein a segment is not assigned in the step of constructing the memory if i=15.

16. The method of claim 10, wherein the sample data is stored by taking modulo of a corresponding segment size with respect to sample data inputted on a segment basis.

17. The method of claim 10, wherein the step of storing the sample data comprises with respect to a specific segment the steps of:

(a) determining whether or not an inputted sample data is an odd sample data in a corresponding segment;

(b) if the inputted sample data is determined to be an odd sample data in a corresponding segment in the step (a), writing the odd sample data at an n^th address of the memory;

(c) after completion of the writing of the odd sample data, determining whether or not a next even sample data is inputted;

(d) if a next even sample data is determined to be inputted in the step (c), reading data of the n^th address of the memory and then converting an upper 4-bit data into the even sample data;

(e) rewriting the even sample data at the n^th address of the memory;

(f) after completion of the step (e), determining whether or not a next odd sample data is inputted

(g) if the next odd sample data is determined to be inputted in the step (f), increasing a memory address by 1 (that is, n=n+1) and then performing the steps (b) to (f) repeatedly; and

(h) if no even data exists in the step (c) or if no odd data exists in the step (g), completing an sample data write operation for a corresponding segment,

wherein the above steps are performed on each segment.

18. The method of claim 10, wherein the step of reading the sample data comprises with respect to a specific segment the steps of:

(a) generating a byte-based memory address according to a time deinterleaving rule determined by the i value;

(b) determining whether sample data to be read from the generated memory address is an even sample data or an odd sample data in a corresponding segment;

(c) if the sample data to be read from the generated memory address is determined to be an even sample data in the step (b), reading out an upper 4-bit data from the generated memory address and masking the remaining lower 4-bit; and

(d) if the sample data to be read from the generated memory address is determined to be an odd sample data in the step (b), reading out an lower 4-bit data from the generated memory address and masking the remaining upper 4-bit.

19. The method of claim 18, wherein whether sample data to be read from the generated memory address is an even sample data or an odd sample data in a corresponding segment is determined in the step (b) by using a segment pointer indicating to what order sample data in a corresponding segment the sample data to be presently read out corresponds.