Controlling electromechanical behavior of structures within a microelectromechanical systems device

• US 20050250235A1
• Filed: 03/25/2005
• Published: 11/10/2005
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Miles, Mark W., Kothari, Manish, Tung, Ming-Hau, Batey, John
• Granted Patent: US 7,781,850 B2
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Claims

1. A MEMS device having a substrate comprising:

an electrode layer formed over the substrate;

a dielectric layer formed over the electrode layer;

a first etch barrier layer formed over the dielectric layer;

a cavity located above the first etch barrier; and

a moving layer located above the cavity.

2. The device of claim 1, wherein the first etch barrier layer comprises aluminum oxide.

3. The device of claim 2, wherein the dielectric layer comprises silicon oxide.

4. The device of claim 3, wherein the device comprises a fourth layer formed between the electrode layer and the first dielectric layer, said fourth layer comprising aluminum oxide.

5. The device of claim 3, wherein the device is an interferometric modulator.

6. The device of claim 3, wherein the device comprises a fourth layer formed between the electrode layer and the first dielectric layer, said fourth layer comprising silicon nitride.

7. The device of claim 2, wherein the dielectric layer comprises silicon nitride.

8. The device of claim 1, additionally comprising a second etch barrier layer formed over the first etch barrier layer.

9. The device of claim 8, wherein the second etch barrier layer comprises silicon oxide.

10. The device of claim 9, wherein the dielectric layer comprises silicon oxide.

11. The device of claim 9, wherein the dielectric layer comprises a charge trapping layer.

12. The device of claim 8, wherein the second etch barrier layer comprises silicon nitride.

13. The device of claim 12, wherein the dielectric layer comprises silicon oxide.

14. The device of claim 12, wherein the dielectric layer comprises silicon nitride.

15. The device of claim 8, wherein the second etch barrier layer comprises titanium.

16. The device of claim 8, wherein the second etch barrier layer comprises molybdenum.

17. The device of claim 8, wherein the second etch barrier layer comprises amorphous silicon.

18. The device of claim 8, wherein the second etch barrier layer has a varying thickness over the surface of the first etch barrier layer.

19. The device of claim 18, wherein the second etch barrier covers only a portion of the first etch barrier layer.

20. The device of claim 7, wherein a sacrificial material fills the cavity.

21. The device of claim 20, wherein the sacrificial material is selectively etchable by a phosphoric/acetic/nitric acid etch relative to the second etch barrier.

22. The device of claim 20, wherein the sacrificial material and the second etch barrier are selectively etchable by XeF₂ relative to the first etch barrier layer.

23. A method of manufacturing a MEMS device, comprising:

depositing an electrode layer on a substrate;

depositing a dielectric layer over the electrode layer; and

depositing an etch stop layer over the dielectric layer.

24. The method of claim 23, wherein the etch stop layer comprises aluminum oxide.

25. The method of claim 24, wherein the dielectric layer comprises silicon oxide.

26. The method of claim 24, wherein the dielectric layer comprises silicon nitride.

27. The method of claim 24, additionally comprising depositing a second layer of aluminum oxide over the electrode layer, wherein the dielectric layer is deposited over the second layer of aluminum oxide.

28. The method of claim 24, additionally comprising:

depositing at least a first sacrificial layer over the etch stop layer;

depositing a reflective layer over the sacrificial layer; and

etching the first sacrificial layer to completely remove the first sacrificial layer, thereby creating an interferometric cavity.

29. The method of claim 28, additionally comprising:

depositing a protective layer over the first sacrificial layer, wherein the first sacrificial layer is deposited over the protective layer;

performing a preliminary etch to remove a portion of the first sacrificial layer, thereby exposing a portion of the protective layer; and

depositing at least a second sacrificial layer over the first sacrificial layer;

wherein the etching the first sacrificial layer to completely remove the first sacrificial layer comprises removing at least a portion of the second sacrificial layer.

30. The method of claim 29, wherein the protective layer comprises silicon oxide.

31. The method of claim 29, wherein the protective layer comprises silicon nitride.

32. The method of claim 29, wherein the protective layer comprises amorphous silicon.

33. The method of claim 29, wherein the protective layer comprises molybdenum.

34. The method of claim 29, wherein the protective layer comprises titanium.

35. The method of claim 29, wherein etching the first sacrificial layer to completely remove the first sacrificial later removes at least a portion of the protective layer.

36. A method of manufacturing a MEMS device, comprising:

depositing an electrode layer on a substrate;

depositing a charge-trapping layer over the electrode layer; and

depositing a first etch barrier layer over the dielectric layer.

37. The method of claim 36, wherein the first etch barrier comprises aluminum oxide.

38. The method of claim 37, wherein the charge-trapping layer comprises silicon nitride.

39. The method of claim 37, wherein the charge-trapping layer comprises tantalum pentoxide.

40. The method of claim 36, additionally comprising:

depositing a second etch barrier layer over the first etch barrier layer;

depositing a first layer of sacrificial material over the second etch barrier layer;

performing a first etch to remove a portion of the first layer of sacrificial material, thereby exposing a portion of the second etch barrier layer;

depositing at least a second layer of sacrificial material over the first layer of sacrificial material and over the exposed portion of the second etch barrier layer;

depositing an electrode over the first and second layers of sacrificial material; and

performing a second etch to remove at least the first and second layers of the sacrificial material, thereby forming an interferometric cavity.

41. The method of claim 40, wherein the second etch barrier layer comprises a material selected from the group consisting of:

silicon oxide, silicon nitride, amorphous silicon, molybdenum, and titanium.

42. The method of claim 40, wherein the first etch is performed using an etchant to which the second etch barrier layer is more resistant than the first sacrificial layer.

43. The method of claim 40, wherein the second etch barrier is at least partially removed during the second etch and the first etch barrier layer is resistant to the second etch.

44. A MEMS device, comprising:

a substrate;

an electrode layer formed over the substrate;

a layer of silicon nitride formed over the electrode layer; and

a layer of aluminum oxide formed over the layer of silicon nitride.

45. The device of claim 44, additionally comprising:

a cavity formed over the layer of aluminum oxide; and

a movable layer formed above the cavity.

46. The device of claim 45, wherein the device is an interferometric modulator.

47. The device of claim 46, additionally comprising a layer of silicon oxide formed over the layer of aluminum oxide.

48. The device of claim 47, wherein the layer of silicon oxide is over the layer of aluminum oxide under posts that support the moveable layer above the cavity.

49. The device of claim 45, additionally comprising a silicon nitride layer formed over the aluminum oxide layer.

50. The device of claim 49, wherein the layer of silicon nitride is over the layer of aluminum oxide under posts that support the moveable layer above the cavity.

51. The device of claim 44, additionally comprising a second layer of aluminum oxide, wherein the second layer of aluminum oxide is formed over the electrode layer, and wherein the silicon nitride layer is formed over the second layer of aluminum oxide.