Semiconductor on insulator structure

• US 20060001094A1
• Filed: 08/29/2005
• Published: 01/05/2006
• Est. Priority Date: 05/21/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 7,528,463 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Claims

1. A semiconductor on insulator structure comprising:

an insulating substrate; and

a semiconductor layer bonded to the insulating substrate, the insulating substrate being a different material than the semiconductor layer, wherein the insulating substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion for the semiconductor layer.

2. The semiconductor on insulator structure of claim 1, wherein the semiconductor layer has a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures.

3. The semiconductor on insulator structure of claim 1, wherein the insulating substrate is a silicon oxycarbide substrate.

4. The semiconductor on insulator structure of claim 1, wherein the semiconductor on insulator structure includes an insulating layer between the semiconductor layer and the insulating substrate.

5. The semiconductor on insulator structure of claim 1, wherein the semiconductor layer is a silicon layer.

6. The semiconductor on insulator structure of claim 1, wherein the semiconductor on insulator structure includes an oxide layer between the semiconductor layer and the insulating substrate.

7. The semiconductor on insulator structure of claim 1, wherein the semiconductor on insulator structure is structured as a wafer.

8. The semiconductor on insulator structure of claim 1, wherein the semiconductor layer includes device circuitry of a dynamic random access memory configured to couple to a processor.

9. An electronic device comprising:

an insulating substrate;

a semiconductor layer bonded to the insulating substrate, the insulating substrate being a different material than the semiconductor layer, wherein the insulating substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion for the semiconductor layer; and

circuitry in the semiconductor layer.

10. The electronic device of claim 9, wherein the semiconductor layer has a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures.

11. The electronic device of claim 9, wherein the insulating substrate is a silicon oxycarbide substrate.

12. The electronic device of claim 9, wherein the semiconductor layer is a silicon layer having a thickness ranging from about 0.1 microns to about 10 microns.

13. The electronic device of claim 9, wherein the semiconductor layer has a thickness ranging from about 0.1 microns to about 10 microns.

14. The electronic device of claim 9, wherein the electronic device includes an insulator layer between the semiconductor layer and the insulating substrate.

15. The electronic device of claim 9, wherein the electronic device includes an oxide layer between the semiconductor layer and the insulating substrate.

16. The electronic device of claim 9, wherein the circuitry includes circuitry of a memory device.

17. The electronic device of claim 9, wherein the circuitry includes a transistor.

18. The electronic device of claim 17, wherein the transistor includes a CMOS device.

19. The electronic device of claim 9, wherein the circuitry includes a bipolar transistor.

20. An electronic device comprising:

a silicon oxycarbide substrate;

a silicon layer bonded to the silicon oxycarbide substrate, wherein the silicon oxycarbide substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion for the silicon layer; and

circuitry in the silicon layer.

21. The electronic device of claim 20, wherein the silicon layer has a thickness ranging from about 0.1 microns to about 10 microns.

22. The electronic device of claim 20, wherein the electronic device includes an oxide layer between the silicon layer and the silicon oxycarbide substrate.

23. The electronic device of claim 20, wherein the circuitry includes circuitry of a memory device.

24. The electronic device of claim 20, wherein the circuitry includes a transistor.

25. The electronic device of claim 20, wherein the circuitry includes a bipolar transistor.

26. An electronic system comprising:

a controller;

a bus; and

an electronic device coupled to the processor by the bus, the electronic device including;

an insulating substrate;

a semiconductor layer bonded to the insulating substrate, the insulating substrate being a different material than the semiconductor layer, wherein the insulating substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion for the semiconductor layer; and

a circuit in the semiconductor layer.

27. The electronic system of claim 26, wherein the semiconductor layer has a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures.

28. The electronic system of claim 26, wherein the insulating substrate is silicon oxycarbide substrate.

29. The electronic system of claim 26, wherein the semiconductor layer is a silicon layer having a thickness ranging from about 0.1 microns to about 10 microns.

30. The electronic system of claim 26, wherein the semiconductor layer has a thickness ranging from about 0.1 microns to about 10 microns.

31. The electronic system of claim 26, wherein the circuitry includes a transistor.

32. The electronic system of claim 26, wherein the circuitry includes a bipolar transistor.

33. The electronic system of claim 26, wherein the circuitry includes circuitry of a memory device.

34. The electronic system of claim 26, wherein the electronic system includes an information handling system.

35. The electronic system of claim 26, wherein the electronic system includes a wireless system.

36. The electronic system of claim 26, wherein the electronic system includes an electro-optic system.

37. An electronic system comprising:

a processor;

a system bus; and

a memory device coupled to the processor by the system bus, the memory device including;

a silicon oxycarbide substrate;

a silicon layer bonded to the silicon oxycarbide substrate, wherein the silicon oxycarbide substrate has a coefficient of thermal expansion that is approximately equal to a coefficient of thermal expansion for the silicon layer; and

a circuit in the silicon layer.

38. The electronic system of claim 37, wherein the silicon layer has a thickness ranging from about 0.1 microns to about 10 microns.

39. The electronic system of claim 37, wherein the memory device includes an oxide layer between the silicon layer and the silicon oxycarbide substrate.

40. The electronic system of claim 37, wherein the electronic system includes an information handling system.