Drift compensation in a flash memory

• US 20060028875A1
• Filed: 08/18/2005
• Published: 02/09/2006
• Est. Priority Date: 07/26/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Ronen, Amir, Avraham, Meir
• Granted Patent: US 7,817,469 B2
• Time in Patent Office: Days
• US Class Current: 365/185.240
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.

Claims

1. A method of managing a plurality of memory cells, comprising the steps of:

(a) obtaining a respective value of at least one environmental parameter of the plurality of memory cells; and

(b) adjusting a respective value of at least one reference voltage of the plurality of memory cells in accordance with said at least one obtained value.

2. The method of claim 1, wherein said at least one environmental parameter includes at least one historical parameter.

3. The method of claim 2, wherein said at least one historical parameter includes a count of program-erase cycles of the plurality of memory cells.

4. The method of claim 2, wherein said at least one historical parameter includes a data retention time of the plurality of memory cells.

5. The method of claim 1, wherein said at least one environmental parameter includes a temperature of the plurality of memory cells.

6. The method of claim 1, wherein said at least one reference voltage includes a read reference voltage.

7. The method of claim 1, wherein said at least one reference voltage includes a program verify reference voltage.

8. The method of claim 1, wherein said adjusting is of respective values of a plurality of said reference voltages, wherein said plurality of said reference voltages includes a plurality of said reference voltages of respective threshold voltage bands, and wherein said adjusting of said respective value of each said reference voltage is effected in a manner specific to said respective threshold voltage band of said each reference voltage.

9. A memory device, comprising:

(a) a plurality of memory cells; and

(b) a controller operative to manage said plurality of memory cells by;

(i) obtaining a respective value of at least one environmental parameter of said plurality of memory cells, and

(ii) adjusting a respective value of at least one reference voltage of said plurality of memory cells in accordance with said at least one obtained value.

10. A method of managing a plurality of memory cells, comprising the steps of:

(a) measuring a statistic of at least some of the memory cells relative to a single respective reference parameter of a reference voltage of the plurality of memory cells; and

(b) adjusting a respective value of said reference voltage in accordance with said measured statistic.

11. The method of claim 10, wherein said reference voltage is a read reference voltage.

12. The method of claim 10, wherein said reference voltage is a program verify reference voltage.

13. The method of claim 10, wherein said statistic is a statistic of threshold voltages of said at least some cells, and wherein said reference parameter is related to a property of a corresponding initial distribution of said threshold voltages.

14. The method of claim 13, wherein said property is a lower bound of said initial distribution.

15. The method of claim 13, wherein said property is a median of said initial distribution.

16. The method of claim 10, further comprising the step of:

(c) programming the memory cells to store data.

17. The method of claim 16, wherein said measuring is delayed relative to said programming by a predetermined wait time.

18. The method of claim 16, further comprising the step of:

(d) selecting said at least some cells in accordance with said data.

19. The method of claim 18, wherein said selecting includes reading said data from the cells, and wherein said reading and said measuring are iterated to select said at least some cells.

20. The method of claim 10, wherein said statistic is measured for all of the cells.

21. A memory device, comprising:

(a) a plurality of memory cells; and

(b) a controller operative to manage said plurality of memory cells by;

(i) measuring a statistic of at least some of said memory cells relative to a single respective reference parameter of a reference voltage of said plurality of memory cells, and

(ii) adjusting a respective value of said reference voltage in accordance with said measured statistic.