Drift compensation in a flash memory

• US 7,817,469 B2
• Filed: 08/18/2005
• Issued: 10/19/2010
• Est. Priority Date: 07/26/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Ronen, Amir, Avraham, Meir
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/206,033
• Publication Number:
  US 20060028875A1
• Time in Patent Office: 1,888 Days
• Field of Search: 365/185.03 X, 365/185.09 O, 365/185.22 X, 365/185.24, 365/185.33, 365/211.X
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.

Claims

1. A method of managing a plurality of memory cells, comprising:

(a) obtaining a value of a data retention time of the plurality of memory cells, each memory cell having a floating gate structure; and

(b) adjusting a respective value of at least one reference voltage of the plurality of memory cells in accordance with said obtained value.

2. The method of claim 1, wherein said at least one reference voltage includes a read reference voltage.

3. The method of claim 1, wherein said at least one reference voltage includes a program verify reference voltage.

4. The method of claim 1, wherein said adjusting is of respective values of a plurality of said reference voltages, wherein said plurality of said reference voltages includes a plurality of said reference voltages of respective threshold voltage bands, and wherein said adjusting of said respective value of each said reference voltage is effected in a manner specific to said respective threshold voltage band of said each reference voltage.

5. A memory device, comprising:

(a) a plurality of memory cells each having a floating gate structure; and

(b) a controller to manage said plurality of memory cells, said controller obtains a value of a data retention time of said plurality of memory cells, and adjusts a respective value of at least one reference voltage of said plurality of memory cells in accordance with said obtained value.

6. A method of managing a plurality of memory cells, comprising:

obtaining a value of a data retention time associated with the memory cells;

calculating a drift correction to a reference voltage for the memory cells based on the obtained value of the data retention time; and

changing a value of the reference voltage by an amount of the calculated drift correction.

7. The method of claim 6, wherein the reference voltage is a read voltage, further comprising decreasing the read voltage in proportion to the calculated drift correction.

8. The method of claim 7, wherein the read voltage is decreased in linear proportion to the calculated drift correction.

9. The method of claim 6, wherein the reference voltage is a verify voltage, further comprising increasing the verify voltage in proportion to the calculated drift correction.

10. The method of claim 9, wherein the verify voltage is increased in linear proportion to the calculated drift correction.

11. The method of claim 6, wherein the drift correction is calculated in accordance with the relationship:

(drift correction)=(data retention coefficient)×

(band-number coefficient)×

(time-since-programmed)+(data retention initial offset);

wherein the data retention coefficient is an empirically determined coefficient that applies to all threshold voltage bands,

wherein the band-number coefficient is an empirically determined coefficient that applies to a particular threshold voltage band,

wherein the time-since-programmed is an elapsed time since a page of memory cells was first programmed, and

wherein the data retention initial offset is an empirically determined constant offset.

12. A memory device, comprising:

a plurality of memory cells; and

a controller to manage the plurality of memory cells, said controller obtains a value of a data retention time associated with the memory cells, obtains a value of a data retention time associated with the memory cells, calculates a drift correction to a reference voltage for the memory cells based on the obtained value of the data retention time, and changes a value of the reference voltage by an amount of the calculated drift correction.

13. The memory device of claim 12, wherein the reference voltage is a read voltage, and the controller decreases the read voltage in proportion to the calculated drift correction.

14. The memory device of claim 12, wherein the reference voltage is a verify voltage, and the controller increases the verify voltage in proportion to the calculated drift correction.

15. The memory device of claim 12, wherein the controller calculates the drift correction in accordance with the relationship:

(drift correction)=(data retention coefficient)×

(band-number coefficient)×

(time-since-programmed)+(data retention initial offset);

wherein the data retention coefficient is an empirically determined coefficient that applies to all threshold voltage bands,

wherein the band-number coefficient is an empirically determined coefficient that applies to a particular threshold voltage band,

wherein the time-since-programmed is an elapsed time since a page of memory cells was first programmed, and

wherein the data retention initial offset is an empirically determined constant offset.