Damascene process using different kinds of metals

• US 20060046456A1
• Filed: 08/15/2005
• Published: 03/02/2006
• Est. Priority Date: 08/25/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: An, Chul-wan
• Application Number:
  US11/204,469
• Publication Number:
  US 20060046456A1
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10

Abstract

The present invention is directed to a damascene process using different kinds of metals is provided. An interlayer dielectric is formed to cover a semiconductor substrate. A contact hole is formed to expose the semiconductor substrate through the interlayer dielectric. A groove is formed to overlap the contact hole. A first barrier metal layer is conformally formed. A first seed layer is conformally formed. A first conductive layer is formed to fill a contact hole below the groove. A second conductive layer is formed to fill the groove. According to the damascene process, a CMP process for a tungsten layer is not needed such that total process cost is reduced and the overall general process is simplified.

Claims

1. A damascene process comprising:

stacking an interlayer dielectric on a semiconductor substrate;

patterning the interlayer dielectric to form a groove and a contact at a bottom of the groove to expose the semiconductor substrate;

conformally forming a first barrier metal layer;

conformally forming a first seed layer;

selectively forming a first conductive layer to fill the contact hole; and

forming a second conductive layer to fill the groove.

3. The damascene process of claim 1, wherein the first conductive layer comprises tungsten.

8. The damascene process of claim 1, wherein the second conductive layer comprises copper.

9. The damascene process of claim 1, further comprising conformally forming a second seed layer before the formation of the second conductive layer,

wherein the formation of the second conductive layer is done using electro-plating.

10. The damascene process of claim 1, wherein the formation of the second conductive layer is done using metal organic chemical vapor deposition (MOCVD).

11. The damascene process of claim 9, further comprising conformally forming a second barrier metal layer after the formation of the first conductive layer.

12. The damascene process of claim 1, wherein the semiconductor substrate further includes a gate electrode disposed on the semiconductor substrate and an impurity implantation region disposed in the substrate at opposite sides adjacent to the gate electrode.

13. The damascene process of claim 1, wherein the semiconductor substrate further includes a gate electrode disposed on the substrate and an impurity implantation region disposed in the substrate at opposite sides adjacent to the gate electrode, the gate electrode being exposed during the formation of the contact hole.

14. The damascene process of claim 1, further comprising performing a planarization process to expose the interlayer dielectric after the formation of the second conductive layer.

15. The damascene process of claim 1, further comprising stacking an etch-stop layer on the semiconductor substrate before stacking the interlayer dielectric,

wherein the formation of the contact hole and the groove comprises:

patterning the interlayer dielectric to form a preliminary contact hole exposing the etch-stop layer over the semiconductor substrate;

patterning the interlayer dielectric to form a groove overlapping the preliminary contact hole; and

removing the etch-stop layer exposed by the preliminary contact hole to form a contact hole exposing the semiconductor substrate.

16. The damascene process of claim 1, wherein the formation of the groove and the contact hole comprises:

partially patterning an upper portion of the interlayer dielectric to form a groove for interconnection; and

patterning the interlayer dielectric beneath the groove to form a contact hole exposing the semiconductor substrate.

2. The damascene process of claim 2, wherein the selective formation of the first conductive layer is done using electro-plating.

4. The damascene process of claim 2, further comprising performing a trimming process before the formation of the second conductive layer.

5. The damascene process of claim 4, wherein the trimming process comprises a radio frequency (RF) etch process using argon (Ar).

6. The damascene process of claim 4, further comprising performing a cleaning process after performing the trimming process.

7. The damascene process of claim 6, wherein the cleaning process is performed using hydrogen fluoride (HF).