Selective scrambler for use in a communication system and method to minimize bit error at the receiver

• US 7,634,694 B2
• Filed: 10/15/2004
• Issued: 12/15/2009
• Est. Priority Date: 10/15/2004
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Green, Christopher M., Ho, Horace C., Knapp, David J.
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): Perez; James M
• Application Number:
  US10/966,254
• Publication Number:
  US 20060083328A1
• Time in Patent Office: 1,887 Days
• Field of Search: 375/312, 375316-317, 375/319, 375295-297, 375/309, 327/100, 327306-307, 341 50-107, 713/181, 714/699, 714/701, 714/751, 714/762, 714/776, 714/777, 380/200, 380/210
• US Class Current: 714/701
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

Claims

1. A circuit for transmitting a sequence of bits, comprising:

a memory;

an output circuit coupled to the memory for scrambling a payload section of a frame that includes the payload section, a preamble section, and a parity section, wherein said scrambling comprises inverting a logic value of at least one of the sequence of bits within the payload section;

an enable circuit coupled to the memory for;

(i) enabling the memory to receive the sequence of bits within the payload section of the frame, and (ii) disabling the memory during times in which the transmitting circuit is presented with the preamble and parity sections of the frame; and

a state machine coupled to the enable circuit for detecting the times during which the transmitting circuit is presented with the preamble and parity sections of the frame.

2. The transmitting circuit of claim 1, wherein the memory comprises a shift register.

3. The transmitting circuit of claim 1, wherein the output circuit is coupled to receive the at least one of the sequence of bits from the memory, invert the logic value, and forward the inverted logic value back to the memory.

4. The transmitting circuit of claim 1, wherein the memory comprises:

n number of flip flops coupled in series;

wherein an input of a first flip flop in the series is coupled to an output of the output circuit; and

wherein an output of an nth flip flop and the n−

1 flip flop in the series is coupled to a pair of inputs of the output circuit.

5. The transmitting circuit of claim 1, wherein the enable circuit and the output circuit each comprise combinatorial logic.

6. The transmitting circuit of claim 1, wherein the enable circuit comprises:

a pair of inputs; and

an output coupled to disable outputs from the memory if the pair of inputs receive at least one signal indicating that the preamble section or the parity section is presented to the transmitting circuit.

7. The transmitting circuit of claim 1, wherein the inverted logic value is that of a first bit within the sequence if the logic values of a next consecutive bit within the sequence and an nth bit within the sequence are dissimilar.

8. The transmitting circuit of claim 1, wherein the output circuit is further coupled for not inverting the logic value of a first bit within the sequence if the logic values of a next consecutive bit within the sequence and an nth bit within the sequence are the same.

9. The transmitting circuit of claim 1, wherein the memory comprises n stages for storing each of a sequence of n bits, and wherein the output circuit comprises:

three inputs coupled to receive a first bit from an nth stage of the n stages, a second bit from a n−

1 stage of the n stages, and an nth bit of the sequence of n bits; and

an output coupled to place the inverted logic value upon an input of a first stage of the n stages.

10. The transmitting circuit of claim 1, further comprising:

a first encoder coupled between the output circuit and a transmission path for encoding the scrambled payload section and placing the encoded and scrambled payload section upon the transmission path; and

a second encoder coupled between the output circuit and the transmission path for encoding the preamble section with a coding violation.

11. The transmitting circuit of claim 10, wherein the first encoder is further coupled for encoding the parity section, which is arranged in a different region within the frame than the payload section and the preamble section, and wherein the parity section is encoded with logic values that when combined with the encoded preamble section and the encoded and scrambled payload section present substantially no DC accumulation within a single said frame when received upon a receiver.

12. The transmitting circuit of claim 11, further comprising a multiplexer coupled for selectively applying the scrambled payload section or the parity section to the first encoder.

13. The transmitting circuit of claim 1, wherein the output circuit prevents a sequence of bits output from the memory from exceeding a number n of bits with the same logic value.

14. A communication system, comprising:

a scrambler coupled to temporarily store n bits of a sequence of bits within a payload section of a frame that includes the payload section, a preamble section, and a parity section, where said scrambler inverts a logic value of a first bit within the sequence if a logic value of a next consecutive bit within the sequence and a logic value of a nth bit within the sequence are dissimilar;

an encoder coupled to an output of the scrambler for coding the n bits;

an enable circuit coupled to the scrambler for;

(i) enabling a memory within the scrambler to receive the n bits within the payload section of the frame, and (ii) disabling the memory during times in which the communication system is presented with the preamble and parity sections of the frame;

a state machine coupled to the enable circuit for detecting the times during which the communication system is presented with the preamble and parity sections of the frame;

a transmission path coupled to an output of the encoder for receiving the coded n bits;

a decoder coupled to the transmission path for decoding the coded n bits; and

a descrambler coupled to temporarily store the decoded n bits as a sequence of decoded bits and invert a logic value of a first bit within the sequence of decoded bits if a logic value of a next consecutive bit and a logic value of an nth bit within the sequence of decoded bits are dissimilar.

15. The communication system as recited of claim 14, wherein the scrambler comprises the memory coupled to temporarily store the n bits within only a payload section of a frame that comprises the payload section, the preamble section and the parity section.

16. The communication system as recited of claim 14, wherein logic one voltage values of the coded n bits transition at twice the frequency as logic zero voltage values.

17. The communication system as recited of claim 14, wherein the coded n bits incur a transition near the beginning of an m clock cycle provided a logic one voltage value occurs during the m+1 clock cycle and the sum of DC voltage values of all coded logic one and logic zero voltages values is skewed toward either the logic one or logic zero voltage value prior to the m clock cycle.

18. The communication system as recited of claim 14, wherein the transmission path is an optical medium.

19. The communication system as recited of claim 14, wherein the encoder is coupled to code an additional m bits within the preamble section of the frame that precedes the n bits within a payload section of the frame, and for coding the m bits with a sequence that is recognizable by the decoder as a coding violation to synchronize the beginning of the frame as well as the payload section within the frame.

20. The communication system as recited of claim 14, wherein the encoder is coupled to code an additional p bits within the parity section of the frame that is subsequent to the n bits within the payload section, and for coding the p bits with a sequence that maintains parity with the n bits within the payload section.