DRAM technology compatible processor/memory chips

• US 20060124981A1
• Filed: 02/06/2006
• Published: 06/15/2006
• Est. Priority Date: 02/26/1999
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Cloud, Eugene H.
• Application Number:
  US11/347,989
• Publication Number:
  US 20060124981A1
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Claims

1. An electronic system, comprising:

an electronic device; and

a processor operatively coupled to electronic device; and

wherein the processor includes at least one programmable logic array including;

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, wherein the stacked capacitor has a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

2. The electronic system of claim 1, wherein the electronic device includes a memory formed on a die common with the processor.

3. The electronic system of claim 1, wherein the processor further comprises:

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane and interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and

wherein the non-volatile memory cells of the second logic plane each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

4. The electronic system of claim 3, wherein the first logic plane and the second logic plane each comprise NOR planes.

5. The electronic system of claim 3, wherein the electronic device and the processor are formed on a same bulk semiconductor substrate, and wherein the electrical contact includes a polysilicon plug.

6. The electronic system of claim 5, wherein the substrate includes a working surface and includes an insulating layer formed on top of an underlying semiconductor.

7. The electronic system of claim 1, wherein the programmable logic array is operatively coupled to a computer system.

8. The electronic system of claim 1, wherein the stacked capacitor includes a fin type capacitor.

9. The electronic system of claim 1, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the MOSFET.

10. The electronic system of claim 3, wherein:

the processor includes at least one register formed from dynamic random access memory cells, and wherein the processor includes at least one function and sequence circuit.

11. The electronic system of claim 3, wherein the processor includes a program circuit that stores a program.

12. The electronic system of claim 11, wherein the program circuit stores the program in an EEPROM.

13. The electronic system of claim 3, wherein the first logic plane includes N address lines and 2N output lines.

14. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being operably coupled to receive the outputs of the first logic plane and interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein at least one of the non-volatile memory cells includes;

a transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

15. The electronic system of claim 14, wherein the implemented logical function includes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

16. The electronic system of claim 14, wherein the first logic plane includes inverters adapted to generate a complement of the input signal.

17. The electronic system of claim 14, wherein the electrical contact includes a polysilicon plug, and wherein the stacked capacitor includes a fin type capacitor.

18. The electronic system of claim 14, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact operatively couples the storage node of the stacked capacitor to the gate of the transistor.

19. The electronic system of claim 18, wherein the transistor is a metal oxide semiconductor field effect transistor.

20. An electronic system, comprising:

an electronic device; and

a processor operatively coupled to the electronic device; and

wherein the processor includes at least one programmable logic array including;

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and

wherein the non-volatile memory cells of the first logic plane each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

21. The electronic system of claim 20, wherein the electronic device includes a memory formed on a substrate common with the processor.

22. The electronic system of claim 20, wherein the processor comprises:

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being adapted to produce a number of logic outputs,

wherein the non-volatile memory cells of the second logic plane each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

23. The electronic system of claim 22, wherein the logic outputs of the second logic plane consist of outputs of at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

24. The electronic system of claim 22, wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.

25. The electronic system of claim 22, wherein the logic outputs of the second logic plane include NAND outputs.

26. The electronic system of claim 22, wherein the cup-shaped stacked capacitor of at least one of the first logic plane and the second logic plane includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

27. The electronic system of claim 22, wherein the first logic plane includes N address lines and 2N output lines.

28. The electronic system of claim 20, wherein the stacked capacitor includes a fin type capacitor.

29. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to the gate of the transistor.

30. The electronic system of claim 29, wherein the gate oxide has a thickness of less than 100 angstroms.

31. The electronic system of claim 29, wherein the gate oxide is adapted to act as a tunneling oxide.

32. The electronic system of claim 29, wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.

33. The electronic system of claim 29, wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.

34. The electronic system of claim 29, wherein the stacked capacitor includes a fin type capacitor.

35. The electronic system of claim 29, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

36. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and

an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

37. The electronic system of claim 36, wherein the bottom plate serves as a storage node.

38. The electronic system of claim 36, wherein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.

39. The electronic system of claim 36, wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.

40. The electronic system of claim 39, wherein the first logic plane includes inverters that generate a complement of the input signal.

41. The electronic system of claim 40, wherein the electrical contact includes a polysilicon plug.

42. The electronic system of claim 41, wherein the stacked capacitor includes a fin type capacitor.

43. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and

a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and

an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.

44. The electronic system of claim 43, wherein the bottom plate serves as a storage node.

45. The electronic system of claim 43, wherein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.

46. The electronic system of claim 43, wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.

47. The electronic system of claim 46, wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.

48. The electronic system of claim 47, wherein the electrical contact includes a polysilicon plug.

49. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells that are interconnected to provide a number of logic outputs; and

a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

50. The electronic system of claim 49, wherein the gate oxide acts as a tunneling oxide.

51. The electronic system of claim 49, wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.

52. The electronic system of claim 49, wherein the first logic plane includes inverters that are adapted to generate complements of the input signal, wherein the electrical contact includes a polysilicon plug, and wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

53. An electronic system with a programmable logic array, comprising:

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic output; and

a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide, the gate oxide being adapted to act as a tunneling oxide;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

54. The electronic system of claim 53, wherein the outputs of the first logic plane include a NOR output and the outputs of the second plane include a NAND output.

55. The electronic system of claim 53, wherein the first logic plane includes N address lines and 2N output lines.

56. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the die includes at least one programmable logic array including;

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile first memory cells arranged in rows and columns that are interconnected to provide a number of first logic outputs; and

a second logic plane having a number of non-volatile second memory cells arranged in rows and columns, the non-volatile second memory cells being adapted to receive the outputs of the first logic plane and that are interconnected to produce a number of second logic outputs,

wherein the first non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

57. The electronic system of claim 56, wherein the implemented logical function includes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

58. The electronic system of claim 56, wherein the first logic plane includes inverters adapted to generate complements of the input signals.

59. The electronic system of claim 56, wherein the electrical contact includes a polysilicon plug.

60. The electronic system of claim 56, wherein the stacked capacitor includes a fin type capacitor.

61. The electronic system of claim 60, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

62. The electronic system of claim 60, wherein the first logic plane includes N address lines and 2N logic outputs.

63. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the processor includes at least one programmable logic array including;

a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide, wherein the gate oxide has a thickness of less than 100 angstroms;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

64. The electronic system of claim 63, wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

65. The electronic system of claim 64, wherein the first logic plane and the second logic plane each comprise NOR planes.

66. The electronic system of claim 63, wherein the logic outputs of the first logic plane include at least one of NOR, OR, AND, NAND;

and the logic outputs of the second logic plane include at least one of NOR, OR, AND, NAND.

67. The electronic system of claim 63, wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.

68. The electronic system of claim 63, wherein the processor includes at least one register formed from dynamic random access memory cells;

and wherein the processor includes at least one function and sequence circuit.

69. The electronic system of claim 63, wherein the processor includes a program circuit that stores a program.

70. The electronic system of claim 69, wherein the program circuit stores the program in an EEPROM.

71. The electronic system of claim 63, wherein the gate oxide acts as a tunneling oxide.

72. The electronic system of claim 63, wherein the first logic plane includes inverters that are adapted to generate complements of the input signal.

73. The electronic system of claim 63, wherein the electrical contact includes a polysilicon plug.

74. The electronic system of claim 63, wherein the stacked capacitor includes a fin type capacitor.

75. The electronic system of claim 63, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

76. The electronic system of claim 63, wherein the stacked capacitor includes a cup-shaped capacitor.