Solder interconnect on IC chip

• US 20060125094A1
• Filed: 06/17/2005
• Published: 06/15/2006
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 8,067,837 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06167 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16106 the bump connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.

Claims

1. (canceled)

2. A semiconductor chip comprising:

a circuit; and

a bump on said circuit, wherein the area of projecting the contact between said bump and said circuit onto a plane is greater than 30,000 μ

m².

3. The semiconductor chip of claim 2, wherein said area is greater than 80,000 μ

m².

4. The semiconductor chip of claim 2, wherein said area is greater than 150,000 μ

m².

5. The semiconductor chip of claim 2, wherein said circuit mainly comprises copper.

6. The semiconductor chip of claim 2, wherein said circuit mainly comprises aluminum.

7. The semiconductor chip of claim 2, wherein said bump has a thickness greater than 5 μ

m.

8. The semiconductor chip of claim 2, wherein said bump has a thickness greater than 1 μ

m.

9. The semiconductor chip of claim 2, wherein the topmost portion of said bump comprises gold.

10. The semiconductor chip of claim 2, wherein the topmost portion of said bump comprises solder.

11. The semiconductor chip of claim 2 further comprising a passivation layer on said circuit, and a semiconductor substrate under said circuit, wherein said bump is on said circuit exposed by an opening in said passivation layer.

12. The semiconductor chip of claim 2 further comprising a passivation layer under said circuit, a metallization structure under said passivation layer and a semiconductor substrate under said metallization structure.

13. A semiconductor chip comprising:

a circuit; and

a bump on said circuit, wherein the area of projecting the contact between said bump and said circuit onto a plane has an extending distance of greater than 500 μ

m.

14. The semiconductor chip of claim 13, wherein said extending distance is greater than 800 μ

m.

15. The semiconductor chip of claim 13, wherein said extending distance is greater than 1,200 μ

m.

16. The semiconductor chip of claim 13 further comprising a passivation layer on said circuit, and a semiconductor substrate under said circuit, wherein said bump is on said circuit exposed by an opening in said passivation layer.

17. The semiconductor chip of claim 13 further comprising a passivation layer under said circuit, a metallization structure under said passivation layer and a semiconductor substrate under said metallization structure.

18. A chip package comprising:

a semiconductor chip;

a circuitry component; and

a bump between said semiconductor chip and circuitry component, wherein said bump has a least cross-sectional area parallel to an active surface of said semiconductor chip, wherein said least cross-sectional area is greater than 30,000 μ

m².

19. The chip package of claim 18, wherein said least cross-sectional area is greater than 80,000 μ

m².

20. The chip package of claim 18, wherein said least cross-sectional area is greater than 150,000 μ

m².

21. The chip package of claim 18, wherein said bump comprises solder.