Techniques for optimizing design of a hard intellectual property block for data transmission

• US 20060125517A1
• Filed: 12/13/2004
• Published: 06/15/2006
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wortman, Curt, Chong, Thow-Pang, Ang, Boon-Jin, van Wageningen, Darren, Mansur, Dan, Burney, Ali
• Granted Patent: US 7,434,192 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Claims

1. A programmable logic integrated circuit comprising a hard intellectual property (HIP) block designed to transmit data along parallel data channels, the hard intellectual property block comprising:

an oversampler that reduces clock skew between a clock signal and data in a first set of parallel data channels;

a down converter coupled to the oversampler that transmits the data from a first set of parallel data channels to a second set of parallel data channels that have less parallel data channels than the first set; and

a channel alignment block coupled to the down converter that aligns corresponding data bits on the second set of parallel data channels.

2. The programmable logic integrated circuit defined in claim 1 wherein the channel alignment block compares data bytes between the data channels to specific patterns to byte align the data channels.

3. The programmable logic integrated circuit defined in claim 1 wherein the down converter transmits data to the second set of parallel data channels at a first clock frequency of the HIP block that is faster than a second clock frequency of data on the first set of parallel data channels.

4. The programmable logic integrated circuit defined in claim 1 wherein the HIP block further comprises:

an input/output interface block that receives data from off-chip and generates the first set of parallel data channels.

5. The programmable logic integrated circuit defined in claim 4 wherein the input/output interface block includes a first deserializer that generates the first set of parallel data channels.

6. The programmable logic integrated circuit defined in claim 4 wherein the HIP block further comprises a transmitter coupled to the channel alignment block that encodes packets of data into a SPI4-2 compatible data protocol;

and a receiver that extracts data packets from SPI4-2 compatible data.

7. The programmable logic integrated circuit defined in claim 6 wherein the HIP block further comprises:

a first FIFO buffer coupled to inputs of the transmitter for performing data for rate adaptation; and

a second FIFO buffer coupled to outputs of the receiver for performing data rate adaptation.

8. The programmable logic integrated circuit defined in claim 7 further comprising:

a set of programmable logic circuits configured as an error generator block that transmits errors to the first FIFO buffer; and

a data interface coupled between the first FIFO buffer in the HIP block and the error generator block.

9. The programmable logic integrated circuit defined in claim 7 further comprising:

a set of programmable logic circuits configured as an error monitor that monitors data output from the second FIFO buffer; and

a data interface coupled between the second FIFO buffer in the HIP block and the error monitor block.

10. A method for performing channel alignment on a hard intellectual property (HIP) block of a programmable logic integrated circuit, the HIP block designed to transmit data along parallel data channels, the method comprising:

oversampling a clock signal to reduce clock skew between the clock signal and the data received on a first set of parallel data channels;

transmitting the data on the first set of parallel data channels to a second set of parallel data channels that have less parallel data channels than the first set; and

aligning corresponding data bits in the second set of parallel data channels using channel alignment circuitry in the HIP block.

11. The method according to claim 10 further comprising:

deserializing serial data to generate the first set of parallel data channels.

12. The method according to claim 10 further comprising:

encoding packets of the data into a SPI4-2 compatible data protocol for transmission outside the integrated circuit.

13. The method according to claim 12 further comprising:

storing data received from logic on the programmable logic integrated circuit in a FIFO before the data is encoded into the SPI4.2 compatible data protocol.

14. The method according to claim 10 further comprising:

extracting data packets from SPI4-2 compatible data received from the channel alignment circuitry.

15. The method according to claim 13 further comprising:

storing the data packets in a FIFO buffer; and

transmitting the data packets to logic on the programmable logic integrated circuit.

16. A programmable logic integrated circuit comprising:

a programmable logic portion comprising programmable logic circuits; and

a hard intellectual property (HIP) block comprising a transmitter that encodes packets of data into a data protocol, and a receiver that extracts data packets from a data stream that is encoded in the data protocol,

wherein the programmable logic circuits are configurable to implement error handling functions for the data processed by the transmitter and the receiver.

17. The programmable logic integrated circuit according to claim 16 wherein the HIP block includes a first FIFO buffer coupled to inputs of the transmitter, and a second FIFO buffer coupled to outputs of the receiver.

18. The programmable logic integrated circuit according to claim 17 wherein a first set of the programmable logic circuits are configurable to function as an error generator that transmits errors to the first FIFO buffer, and a second set of the programmable logic elements are configurable to function as an error monitor that receives data packets from the second FIFO buffer.

19. The programmable logic integrated circuit according to claim 18 wherein the HIP block further comprises a first channel alignment block coupled to inputs of the transmitter, and a second channel alignment block coupled to inputs of the receiver.

20. The programmable logic integrated circuit according to claim 19 wherein the HIP block further comprises a first down converter coupled to inputs of the first channel alignment block, and a second down converter coupled to inputs of the second channel alignment block.

21. The programmable logic integrated circuit according to claim 16 further comprising an input/output interface that receives data from off-chip and generates two sets of parallel data channels that are transmitted to the HIP block.

22. The programmable logic integrated circuit according to claim 21 wherein the input/output interface is operable as a serializer and a deserializer.

23. The programmable logic integrated circuit according to claim 16 wherein the transmitter encodes packets of data into a SPI4-2 data protocol, and the receiver that extracts data packets from a data stream that is encoded in the SPI4-2 data protocol.

24. The programmable logic integrated circuit according to claim 18 further comprising a first data interface coupled between the first FIFO buffer and the error generator, and a second data interface coupled between the second FIFO buffer and the error monitor.

25. The programmable logic integrated circuit according to claim 16 wherein the programmable logic integrated circuit is part of a system that includes a processing unit.

26. A method for handling errors in a hard intellectual property block on a programmable logic integrated circuit, the method comprising:

encodes packets of data into a data protocol for transmission off chip using a transmitter;

extracting data packets from a data stream using a receiver, the data stream being encoded in the data protocol; and

implementing error handling functions for the data processed by the transmitter and the receiver using programmable logic circuits.

27. The method defined in claim 26 wherein the transmitter encodes the packets of data into a SPI4-2 data protocol, and the receiver extracts the data packets from the data stream that is encoded in the SPI4-2 data protocol.

28. The method defined in claim 26 wherein implementing the error handling functions further comprises generating errors that are transmitted to a first FIFO buffer, and monitoring errors in data packets received from a second FIFO buffer.

29. A method for routing clock signals on a programmable integrated circuit, the method comprising:

transmitting a first data signal and a first clock signal to a HIP block on the integrated circuit;

driving a second data signal and the first clock signal out of the HIP block to an array of logic elements on the programmable integrated circuit; and

receiving the second data signal and the first clock signal at the array of logic elements.

30. The method defined in claim 29 further comprising:

transmitting a second clock signal to the HIP block; and

driving the second clock signal out of the HIP block to the array of logic elements.

31. A programmable logic integrated circuit comprising:

a programmable logic portion comprising programmable logic circuits; and

a hard intellectual property (HIP) block comprising a transmitter that encodes packets of data into a data protocol, and a receiver that extracts data packets from a data stream that is encoded in the data protocol,

wherein a first set of the programmable logic circuits are configurable to implement a FIFO buffer for storing data transmitted between the FIFO buffer and the HIP block.

32. The programmable logic integrated circuit according to claim 31 wherein a second set of the programmable logic circuits are configurable to function as an error marking logic block coupled between the FIFO buffer and the HIP block.

33. The programmable logic integrated circuit according to claim 31 wherein the first set of programmable logic circuits are configured to function as N FIFO buffers that each store data for only one channel of data.

34. The programmable logic integrated circuit according to claim 31 wherein the first set of programmable logic circuits are configured to function as a single FIFO buffer that stores data for multiple channels of data.