Capacitor structure and fabricating method thereof

• US 20060138517A1
• Filed: 12/28/2005
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Columba Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Dongbuanam Semiconductor, Inc. (DB HiTek Co., Ltd.)
• Inventors: Choi, Chee Hong
• Granted Patent: US 7,385,241 B2
• Time in Patent Office: Days
• US Class Current: 257/307
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.

Claims

1. A capacitor, comprising:

a first electrode wall perpendicular to a semiconductor substrate, including a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts;

a second electrode wall perpendicular to the semiconductor substrate, including a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts; and

at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall.

2. The capacitor of claim 1, wherein the plurality of first and second conductive layers comprise at least one member of the group consisting of copper, aluminum, and tungsten.

3. The capacitor of claim 1, wherein the plurality of first and second contacts comprise at least one member of the group consisting of copper, aluminum, and tungsten.

4. The capacitor of claim 1, wherein the first electrode wall, the second electrode wall, and the at least one dielectric layer are formed on an isolation region of the semiconductor substrate.

5. A method for forming a capacitor in a semiconductor device, comprising the steps of:

(a) forming a dielectric layer;

(b) forming at least two trenches in the dielectric layer, the at least two trenches being separated from each other; and

(c) filling a conductive layer in the at least two trenches;

(d) repeating steps (a) to (c) to form at least two electrode walls perpendicular to a main surface of a semiconductor substrate, each electrode wall having multiple conductive layers stacked over each other, wherein the corresponding conductive layers of the at least two electrode walls being separated from each other by the corresponding dielectric layers.

6. The method of claim 5, further comprising forming a contact hole in each of the at least two trenches, wherein filling the conductive layer further comprises filling the conductive layer in the contact holes in the at least two trenches.

7. The method of claim 5, wherein filling the conductive layer comprises filling Cu in the at least two trenches.

8. The method of claim 5, further comprising forming a barrier metal layer on the dielectric layer, before filling a conductive layer in the at least two trenches.

9. A capacitor, comprising:

a first electrode wall perpendicular to a main surface of a semiconductor substrate;

a second electrode wall perpendicular to the main surface of the semiconductor substrate, and separated from the first electrode wall by a predetermined distance; and

a dielectric layer between the first and second electrode walls.

10. The capacitor of claim 9, wherein the first and second electrode walls include multiple metallization layers.

11. The capacitor of claim 10, wherein the multiple metallization layers include at least one member of the group consisting of aluminum, copper, and tungsten.