Interconnection structure through passive component

• US 20060158863A1
• Filed: 05/04/2005
• Published: 07/20/2006
• Est. Priority Date: 01/19/2005
• Status: Abandoned Application

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Hsu, Chi-Hsing
• Application Number:
  US11/122,656
• Publication Number:
  US 20060158863A1
• Time in Patent Office: Days
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/171 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/023 : using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/145 : Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2201/10636 : Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

An interconnection structure through passive component is provided. The interconnection structure through passive component comprises a first substrate, a second substrate, a plurality of conductive blocks, and at least one passive component. Wherein, the second substrate is disposed on the first substrate. Additionally, the conductive blocks and the passive component are disposed between the first substrate and the second substrate. The first substrate is structurally and electrically connected to the second substrate by the conductive blocks and the passive component.

Claims

1. An interconnection structure through passive component, comprising:

a first substrate;

a second substrate disposed on the first substrate;

a plurality of conductive blocks disposed between the first substrate and the second substrate, wherein the first substrate is structurally and electrically connected to the second substrate by the conductive blocks; and

at least a first passive component disposed between the first substrate and the second substrate, wherein the first substrate is structurally and electrically connected to the second substrate by the first passive component.

2. The interconnection structure through passive component of claim 1, wherein at least an electrode of the first passive component is electrically connected to the first substrate and the second substrate.

3. The interconnection structure through passive component of claim 1, wherein at least an electrode of the first passive component is electrically connected to the first substrate, and at least another electrode of the first passive component is electrically connected to the second substrate.

4. The interconnection structure through passive component of claim 1, wherein the first passive component is a panel-shape passive component.

5. The interconnection structure through passive component of claim 4, wherein the panel shape passive component has a plurality of electrodes separately disposed on two opposite surfaces thereof.

6. The interconnection structure through passive component of claim 1, wherein the first substrate is a package substrate, the second substrate is a chip, and the conductive blocks are bumps.

7. The interconnection structure through passive component of claim 1, wherein the first substrate is a printed circuit board, the second substrate is a chip, and the conductive blocks are bumps.

8. The interconnection structure through passive component of claim 1, wherein the first substrate is a printed circuit board, the second substrate is a package substrate, and the conductive blocks are conductive balls.

9. The interconnection structure through passive component of claim 8, further comprising a chip disposed on the second substrate and electrically connected to the second substrate.

10. The interconnection structure through passive component of claim 9, further comprising a plurality of bumps disposed between the second substrate and the chip, wherein the chip is electrically connected to the second substrate by the bumps.

11. The interconnection structure through passive component of claim 10, further comprising at least a second passive component disposed between the second substrate and the chip, wherein the chip is electrically connected to the second substrate by the second passive component.

12. The interconnection structure through passive component of claim 11, wherein at least an electrode of the second passive component is electrically connected to the second substrate and the chip.

13. The interconnection structure through passive component of claim 11, wherein at least an electrode of the second passive component is electrically connected to the second substrate, and at least another electrode of the second passive component is electrically connected to the chip.

14. An interconnection structure through passive component, comprising:

a printed circuit board;

an electric package disposed on the printed circuit board;

a plurality of conductive blocks disposed between the printed circuit board and the electric package, wherein the printed circuit board is structurally and electrically connected to the electric package by the conductive blocks; and

at least a first passive component disposed between the printed circuit board and the electric package, wherein the printed circuit board is structurally and electrically connected to the electric package by the first passive component.

15. The interconnection structure through passive component of claim 14, wherein at least an electrode of the first passive component is electrically connected to printed circuit board and the electric package.

16. The interconnection structure through passive component of claim 14, wherein at least an electrode of the first passive component is electrically connected to the printed circuit board, and at least another electrode of the first passive component is electrically connected to the electric package.

17. The interconnection structure through passive component of claim 14, wherein the first passive component is a panel-shape passive component.

18. An interconnection structure through passive component, comprising:

a first substrate;

a second substrate disposed on the first substrate; and

at least a passive component disposed between the first substrate and the second substrate, wherein the first substrate is structurally and electrically connected to the second substrate by the first passive component.

19. The interconnection structure through passive component of claim 18, wherein at least an electrode of the first passive component is electrically connected to the first substrate and the second substrate.

20. The interconnection structure through passive component of claim 18, wherein at least an electrode of the first passive component is electrically connected to the first substrate, and at least another electrode of the first passive component is electrically connected to the second substrate.

21. The interconnection structure through passive component of claim 18, wherein the first substrate is a package substrate, and the second substrate is a chip.

22. The interconnection structure through passive component of claim 18, wherein the first substrate is a printed circuit board, and the second substrate is a chip.

23. The interconnection structure through passive component of claim 18, wherein the first substrate is a printed circuit board, and the second substrate is a package substrate.