Semiconductor device

• US 20060163713A1
• Filed: 01/20/2006
• Published: 07/27/2006
• Est. Priority Date: 01/25/2005
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tokunaga, Shinya
• Application Number:
  US11/335,514
• Publication Number:
  US 20060163713A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

In an SiP constituted by laminating a plurality of chips, it is an object to reduce a thickness of the SiP without damaging a strength of a chip on an upper side and deteriorating a reliability due to dicing in the case in which the chip on the upper side is larger than a chip on a lower side. A spot facing portion is provided by etching in the vicinity of a center of a bottom face of a chip on an upper side having a circuit formation surface to be a top face, and a chip on a lower side is disposed on an inside of the spot facing portion.

Claims

1. A semiconductor device, comprising:

a first semiconductor substrate;

a second semiconductor substrate; and

an external connecting terminal, connected to the first or second semiconductor substrate;

wherein at least a part of the first semiconductor substrate is accommodated in a concave portion formed by anisotropic etching on a surface of the second semiconductor substrate.

2. The semiconductor device according to claim 1, wherein the second semiconductor substrate is provided with the concave portion in such a manner that at least a part of a peripheral part thereof is thicker than the other portions.

3. The semiconductor device according to claim 1, wherein the concave portion is formed by a bottom face which is parallel with a main surface of the second semiconductor substrate and a side surface surrounding the bottom face, and the side surface is an inclined face.

4. The semiconductor device according to claim 3, wherein the inclined face is a predetermined crystal face.

5. The semiconductor device according to claim 1, wherein the first semiconductor substrate is fixed to the concave portion of the second semiconductor substrate through an adhesive layer.

6. The semiconductor device according to claim 1, wherein a plurality of concave portions is formed on the second semiconductor substrate and the first semiconductor substrates are fixed to the concave portions one by one.

7. The semiconductor device according to claim 4, wherein the second semiconductor substrate is a silicon substrate and the inclined face is a {111} plane.

8. The semiconductor device according to claim 1, wherein the first semiconductor substrate is a first chip which is laminated and connected onto an interposer and has a circuit portion on a bottom face, and

the second semiconductor substrate is a second chip mounted on the first chip to cover at least a part of the first chip.

9. The semiconductor device according to claim 8, wherein the second chip is connected to the interposer through a bonding wire, and

the first and second chips are accommodated in a resin package together with the bonding wire.

10. The semiconductor device according to claim 9, wherein the second chip has a height of a thick part of a spot facing portion from the interposer which is almost equal to that of the first chip from the interposer.

11. The semiconductor device according to claim 9, wherein the second chip has a height of a thick part of a spot facing portion from the interposer which is greater than that of the first chip from the interposer.

12. The semiconductor device according to claim 9, wherein the first chip is disposed in such a manner that a center thereof is almost coincident with a center of the interposer;

the second chip is disposed in such a manner that a center thereof is shifted from the center of the interposer; and

a spot facing portion of the second chip is provided in a shifted position from the center of the second chip in such a manner that the first chip can be disposed on an inside of the spot facing portion.

13. The semiconductor device according to claim 9, wherein the second chip has thick peripheral parts for all sides thereof.

14. The semiconductor device according to claim 9, wherein the second chip has at least one of sides which is shorter than a side in the same direction in the first chip.

15. The semiconductor device according to claim 9, further comprising:

a third chip, laminated on the interposer and having a circuit portion on a bottom face, the second chip being provided with another spot facing portion which is different from the spot facing portion, and

the third chip having at least a part disposed on an inside of the another spot facing portion.

16. The semiconductor device according to claim 9, wherein a trench portion is provided in such a manner that a height of at least a partial region in a thick part of a spot facing portion from the interposer is greater than a height of the first chip from the interposer.

17. The semiconductor device according to claim 16, wherein the trench portion is uniformly provided on each side of a peripheral part of the spot facing portion.

18. The semiconductor device according to claim 16, wherein a plurality of trench portions is provided and has at least two depths.

19. The semiconductor device according to claim 8, wherein the first semiconductor substrate is a first chip having a circuit portion on the concave portion side,

the second semiconductor substrate is a second chip covering at least a part of the first chip and laminated and connected onto the interposer, and

the first chip is directly connected to the second chip in the concave portion and is connected to the interposer through the second chip.