Hybrid type semiconductor integrated circuit and method of manufacturing the same

• US 20060180898A1
• Filed: 02/16/2006
• Published: 08/17/2006
• Est. Priority Date: 02/17/2005
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), University of Tokyo
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), University of Tokyo
• Inventors: Suzuki, Kazuhiro, Takahashi, Kazuhiro, Funaki, Hideyuki, Toshiyoshi, Hiroshi, Naruse, Yujiro
• Application Number:
  US11/356,413
• Publication Number:
  US 20060180898A1
• Time in Patent Office: Days
• US Class Current: 257/619
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0778 Topology for facilitating the monolithic integration not provided for in B81C2203/0764 - B81C2203/0771
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A hybrid type semiconductor integrated circuit includes a semiconductor active region provided in a first area of a substrate; an insulating region surrounding side surfaces of the semiconductor active region; a mechanical electrode provided in a second area adjacent to the first area and surrounded by a part of the insulating region and a trench; and a interconnection layer one end of which is connected to the mechanical electrode and of which the other end extends to the semiconductor active region via a part of the insulating region.

Claims

1. A hybrid type semiconductor integrated circuit comprising:

a semiconductor active region provided in a first area of a substrate;

an insulating region surrounding side surfaces of the semiconductor active region;

a mechanical electrode provided in a second area of the substrate adjacent to the first area and surrounded by a part of the insulating region and a trench; and

an interconnection layer one end of which is connected to the mechanical electrode and the other end of which extends to the semiconductor active region via a part of the insulating region.

2. The integrated circuit of claim 1, wherein the insulating region includes an insulating trench and an insulator buried in the insulating trench.

3. The integrated circuit of claim 1, wherein the insulating region is a selective oxide film on the semiconductor active region.

4. The integrated circuit of claim 1, wherein the substrate is a semiconductor substrate or an insulating substrate;

and the semiconductor active region is a mono-crystal semiconductor layer provided on the substrate via the insulator.

5. The integrated circuit of claim 1, further comprising:

a mechanical drive system provided in the second area and operated in response to a drive signal applied to the mechanical electrode; and

a drive circuit provided in the first area and generating the drive signal.

6. A hybrid type semiconductor integrated circuit comprising:

a first semiconductor active region provided in a first area of a substrate and including a semiconductor element;

a second semiconductor active region provided in a second area of the substrate adjacent to the first area;

an insulating region surrounding side surfaces of the first and second semiconductor active regions;

a mechanical electrode provided in a third area adjacent to the second area and surrounded not only by a part of the insulating region extending on the side surface of the second area but also by a trench;

a first interconnection layer one end of which is connected to the second semiconductor active region and of which the other end extends to the first semiconductor active region; and

a second interconnection layer of one end which is connected to the mechanical electrode and of which the other end extends to the one end of the first interconnection layer on the second semiconductor active region via a part of the insulating region.

7. The integrated circuit of claim 6, wherein the insulating region includes an insulating trench and an insulator embedded in the insulating trench.

8. The integrated circuit of claim 6, wherein the insulating region is a selective oxide film on the first and second semiconductor active regions.

9. The integrated circuit of claim 6, wherein the substrate is a semiconductor substrate or an insulating substrate;

and the first and second semiconductor active regions are a mono-crystal semiconductor layer provided on the chip via the insulator.

10. The integrated circuit of claim 6, further comprising an MEMS provided in the third area and activated in response to a drive signal supplied to the mechanical electrode;

a drive circuit generating a drive signal and a test circuit inspecting the operation of the drive circuit, both of which are provided in the first area; and

an external test terminal provided in the second area, and extending from the drive circuit via the test circuit.

11. A method of manufacturing a hybrid type semiconductor integrated circuit, the method comprising:

forming an insulating region on a semiconductor layer of a substrate in accordance with a profile of a first area, and forming a semiconductor active region, the semiconductor active region being surrounded by the insulating region;

forming an interconnection layer, the interconnection layer passing over a part of the insulating region and extending from the semiconductor active region to a part of a second area adjacent to the first area of the semiconductor layer;

forming a trench, in the second area, around the semiconductor layer to which the interconnection layer is connected and a part of the insulating region; and

forming a mechanical electrode whose side surfaces are surrounded by the trench and a part of the insulating region.

12. The method of claim 11, wherein the interconnection layer is made after the insulating region is completed;

and the trench is made after the completion of the interconnection layer.

13. The method of claim 11, wherein the insulating region includes an insulating trench extending along the profile of the first area of the semiconductor layer;

and an insulator is buried in the insulating trench.

14. The method of claim 13, wherein the insulating trench and the trench are made by an anisotropic etching process.

15. A method of manufacturing a hybrid type semiconductor integrated circuit, the method comprising:

forming an insulating region on a semiconductor layer of a substrate in accordance with profiles of adjacent first and second areas, and forming a first semiconductor active region in the first area and a second semiconductor active region in the second area, the first and second semiconductor active regions being surrounded by the insulating region;

forming a first interconnection layer one end of which is positioned in the second semiconductor active region and of which the other end extends to the first semiconductor active region;

forming a second interconnection layer, one end of which is connected to the first interconnection layer and the other end of which extends from the second semiconductor active region, passes over a part of the insulating region, and is connected to a part of a third area adjacent to the second area of the semiconductor layer; and

forming a trench, in the second area, around the semiconductor layer to which the interconnection layer is connected and a part of the insulating region, and forming a mechanical electrode whose side surfaces are surrounded by the trench and a part of the insulating region.

16. The method of claim 15, wherein the first interconnection layer is made after completion of the insulating region, and after simultaneously forming the first and second semiconductor active regions;

the second interconnection layer is made after the first interconnection layer; and

the trench is made after the second interconnection layer.

17. The method of claim 16, wherein, a test probe is brought into contact with the completed first or second interconnection layer in order to check circuits formed in the first semiconductor active region.

18. The method of claim 17, wherein the substrate is removed from the second or third area where the mechanical electrode is completed.

19. The method of claim 15, wherein the insulating region includes an insulating trench formed in accordance with the profiles of the first and second areas of the semiconductor layer, and an insulator is buried in the insulating trench.

20. The method of claim 19, wherein the insulating trench and the trench are made by an anisotropic etching process.