Integrated circuit transformer devices for on-chip millimeter-wave applications

• US 20060226510A1
• Filed: 04/08/2005
• Published: 10/12/2006
• Est. Priority Date: 04/08/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Shlafman, Shlomo, Goren, David, Sheinman, Benny, Pfeiffer, Ullrich R.
• Granted Patent: US 7,427,801 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 3/26 Push-pull amplifiers; Phase-splitters therefor duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30
• CPC Class Codes: H03F 3/45089 Non-folded cascode stages
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.

Claims

1. An integrated circuit transformer, comprising:

a substrate;

a ground shield formed on the substrate;

a primary conductor comprising an elongated conductive strip; and

a secondary conductor comprising an elongated conductive strip;

wherein the primary conductor and the secondary conductor are aligned to form a coupled-wire structure that is disposed adjacent to the ground shield; and

wherein the ground shield comprises a pattern of close-ended parallel elongated slots that are disposed orthogonal to the primary and secondary conductors, and wherein the ground shield comprises edge regions that provide current return paths that are collinear to the primary and secondary conductors.

2. The integrated circuit transformer of claim 1, wherein the ground shield, the primary conductor and the secondary conductor are disposed on different layers of an integrated circuit and aligned to form a stacked structure.

3. The integrated circuit transformer of claim 2, further comprising:

a first insulation layer disposed between the ground shield and secondary conductor; and

a second insulation layer disposed between the secondary conductor and the primary conductor.

4. The integrated circuit transformer of claim 1, wherein the ground shield, and primary and secondary conductors are formed from different BEOL (back end of line) metallization layers.

5. The integrated circuit transformer of claim 1, wherein the primary and secondary conductors have lengths and widths that are the same.

6. The integrated circuit transformer of claim 1, wherein the primary conductor has a thickness that is greater than a thickness of the secondary conductor.

7. A semiconductor IC (integrated circuit) chip, comprising:

an integrated circuit comprising a transformer, wherein the transformer comprises;

a ground shield;

a primary conductor comprising at least one elongated conductive strip;

a secondary conductor comprising at least one elongated conductive strip;

wherein the primary conductor and the secondary conductor are aligned to form a coupled-wire structure that is disposed adjacent to the ground shield; and

wherein the ground shield comprises a pattern of close-ended parallel elongated slots that are disposed orthogonal to the primary and secondary conductors, and edge regions that provide current return paths that are collinear to the primary and secondary conductors.

8. The IC chip of claim 7, wherein the ground shield, the primary conductor and the secondary conductor are disposed on different layers and aligned to form a stacked structure.

9. The semiconductor IC chip of claim 7, wherein the transformer is implemented as a resonant tuning circuit.

10. The semiconductor IC chip of claim 9, wherein the transformer is tuned to provide resonance at a frequency of 20 GHz or greater.

11. The semiconductor IC chip of claim 7, wherein the integrated circuit comprises an amplifier.

12. The semiconductor IC chip of claim 11, wherein the transformer is connected to an input or an output of the amplifier.

13. The semiconductor IC chip of claim 11, wherein the amplifier comprises a differential push-pull amplifier, wherein the primary conductor is connected between differential output nodes of the amplifier, and wherein a DC bias voltage is applied to the primary conductor.

14. The semiconductor IC chip of claim 7, wherein the integrated circuit is a power combiner circuit.

15. The semiconductor IC chip of claim 14, wherein the primary conductor of the transformer comprises a plurality of separate elongated conductive strips and wherein the secondary conductor of the transformer comprises a plurality of elongated conductive strips that are serially connected to each other, and wherein each separate elongated conductive strip of the primary conductor is aligned to one of the serially connected elongated conductive strips of the secondary conductor.

16. The semiconductor chip of claim 15, wherein each separate elongated conductive strip of the primary conductor is connected between output nodes of a differential amplifier.

17. The semiconductor IC chip of claim 14, wherein the transformer comprises a ring-like layout pattern.

18. The semiconductor IC chip of claim 15, further comprising a DC supply voltage network comprising supply voltage connections to center regions of each separate elongated conductive strip of the primary conductor.

19. The semiconductor IC chip of claim 7, wherein the integrated circuit transformer is implemented as a BALUN.

20. A method of fabricating a semiconductor device, comprising forming a ground shield, a primary conductor and a secondary conductor, wherein forming the ground shield comprises patterning a layer of conductive material to form close-ended parallel elongated slots that are disposed orthogonal to the primary and secondary conductors, and edge regions that provide current return paths collinear to the primary and secondary conductors.

21. The method of claim 20, wherein the ground shield, primary conductor and secondary conductor are formed on different layers of an integrated circuit to form a stacked transformer device.

22. The method of claim 21, wherein the ground shield, the primary conductor and secondary conductor are formed from different metallization layers using a BEOL process.

23. A computer implemented method for integrated ciruit design and simulation, comprising:

generating a virtual model of a circuit using a model for each component of the circuit, wherein at least one model comprises a lumped equivalent circuit representation of an integrated circuit transformer structure having stacked primary and secondary conductors over a groud planewith, in which conductor length is a user-specified parameter;

performing a simulation of the circuit based on one or more user-specified parameter values for conductor length; and

presenting results of the simulation.

24. The method of claim 23, wherein the lumped equivalent circuit representation of the integrated transformer comprises an RLC filter network.

25. The method of claim 24, wherein generating a virtual model comprises:

providing a user interface that allows a user to build a schematic depiction of the circuit using schemtic icon depictions of the circuit components; and

obtaining a model corresponding to each schematic icon depiction from a libray of predefined models.

26. The method of claim 24, wherein generating a virtual model comprises:

providing a user interface that allows a user to build a 3D circuit layout representation of the circuit;

performing a 3D EM analysis of the 3D circuit; and

generating a equivalent model for each circuit component using results of the 3D EM analysis.